Naoharu Shimomura

Spin transfer switching in TbCoFe∕CoFeB∕MgO∕CoFeB∕TbCoFe magnetic tunnel junctions with perpendicular magnetic anisotropy

Spin transfer (ST) switching in the TbCoFe∕CoFeB∕MgO∕CoFeB∕TbCoFe magnetic tunnel junction (MTJ) was studied. The TbCoFe∕CoFeB free layer with a large coercive field of 1.2kOe and a large thermal stability factor of 107 at room temperature was switched by a 100ns pulse current with a current density of 4.7MA∕cm2. This is the first report of ST switching in a MTJ with perpendicular magnetic anisotropy. The temperature dependence of the coercive field was also investigated to estimate the magnetic anisotropy in the case of rising temperature due to the Joule heating effect. The measured coercive field at 87°C, which was the simulated temperature during the switching pulse current, was about 0.34kOe. The ratio of the switching current density to the coercive field under the switching current in the MTJ with the TbCoFe∕CoFeB free layer is smaller than that in a typical MTJ with an in-plane magnetized CoFeB free layer. This result indicates that a MTJ with perpendicular magnetic anisotropy is advantageous for ...

Lower-current and fast switching of a perpendicular TMR for high speed and high density spin-transfer-torque MRAM

We investigate extremely low programming current and fast switching time of a perpendicular tunnel-magnetoresistance (P-TMR) for spin-transfer torque using a P-TMR cell of 50 nm-diameter. A L10-crystalline ordered alloy is used as a free layer that has excellent thermal stability and a damping constant of about 0.03. The programming current of 49 uA and the switching time of 4 nsec are also demonstrated.

A 64Mb MRAM with clamped-reference and adequate-reference schemes

In order to realize a sub-Giga bit scale NVRAM, the novel MRAM based on the spin-transfer-torque (STT) switching has been intensively investigated due to its excellent scalability compared with a conventional magnetic field induce switching MRAM [1]. However, the memory cell size of STT-MRAM reported so far is still over 1µm2, and the memory capacity is limited to 32Mbit even in almost 100mm2 die size [2]. The large cell size is due to the large switching current of MRAM cells. In order to reduce the cell size, we have proposed the perpendicular tunnel magnetoresistance (P-TMR) device, and have confirmed its high potential to achieve lower switching current [3]. In this paper, a 64Mb STTMRAM with the P-TMR device having the circuit techniques to maximize operational margin is described.

Progress of STT-MRAM technology and the effect on normally-off computing systems

In this paper, the progress of P-MTJs is reviewed and prospects for the normally-off memory hierarchy based on new results are discussed.

Impact of ultra low power and fast write operation of advanced perpendicular MTJ on power reduction for high-performance mobile CPU

We demonstrated lower power consumption of mobile CPU by replacing high-performance (HP)-SRAMs with spin transfer torque (STT)-MRAMs using perpendicular (p)-MTJ. The key points that enable the low power consumption are adapting run time power gating architecture (shown in Fig. 1), and satisfying both fast and low-power writing, namely, 3 nsec and 0.09 pJ, of p-MTJ cell (shown in Fig. 3). As shown in Table 1, only our developed p-MTJ has achieved 3 nsec, 0.09 pJ. Thanks to the fast and low-power p-MTJ, the power consumption of cache memory could be reduced by over 80% without degradation of performance.

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture

Nonvolatile memory, spin-transfer torque magnetoresistive RAM (STT-MRAM) is being developed to realize nonvolatile working memory because it provides high-speed accesses, high endurance, and CMOS-logic compatibility. Furthermore, programming current has been reduced drastically by developing the advanced perpendicular STT-MRAM [1]. Several-megabit STT-MRAM with sub-5ns operation is demonstrated in [2]. Advanced perpendicular STT-MRAM achieve ~3× power saving by reducing leakage current in memory cells compared with SRAM for last level cache (LLC) [3]. Such high-speed RAM applications, however, entail several issues: the probability of read disturbance error increases and the active power of STT-MRAM must be decreased for higher access speed. Moreover, the leakage power of peripheral circuits must be decreased, because the high-speed RAM requires high-performance transistors having high leakage current in peripheral circuitry [4], limiting the energy efficiency of STT-MRAM. To resolve these issues, this paper presents STT-MRAM circuit designs: a short read-pulse generator with small overhead using hierarchical bitline for eliminating read disturbance, a charge-optimization scheme to avoid excessive active charging/discharging power, and ultra-fast power gating and power-on adaptive to RAM status for reducing leakage power.

Novel hybrid DRAM/MRAM design for reducing power of high performance mobile CPU

This paper presents novel DRAM/MRAM hybrid memory design that enables effective power reduction for high performance mobile CPU. Power reduction by about 60% of SRAM-based cache while application is running can be achieved with D-MRAM-based cache memory in CPU. This result is attributable to both novel D-MRAM memory design and lowest programming energy, 0.09pJ, of advanced p-MTJ with ultra-high speed write and low power write (3ns, 50uA).

Future prospects of MRAM technologies

This paper presents a review and future prospects for the tunnel magnetoresistance (TMR) effect in magnetic tunnel junction (MTJ) and spin manipulation technologies such as spin-transfer torque (STT) for magnetoresistive random access memory (MRAM). Major challenges for ultrahigh-density STT-MRAM with perpendicular magnetization and novel functional devices related to MRAM are discussed.

Ion Beam Etching Technology for High-Density Spin Transfer Torque Magnetic Random Access Memory

A spin transfer torque magnetoresistive random access memory (STT-MRAM) is the most promising candidate for a non-volatile random access memory, because of its scalability, high-speed operation, and unlimited read/write endurance. An ion beam etching (IBE) is one of the promising etching methods for a magnetic tunnel junction (MTJ) of the STT-MRAM, because it has no after-corrosion and oxidation problems. In this work, we developed the multiple-step wafer-tilted IBE using computer calculation. Using optimized multiple-step IBE conditions, we fabricated MTJs without barrier-short defects.

Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU

This paper presents a novel nonvolatile last level cache (LLC) based on the advanced perpendicular STT-MRAM to reduce the total power consumption of LLC. The presented LLC has novel readout circuit with the dual-sensing salvation scheme that enhances reliability of STT-MRAM along with typical error-correcting code (ECC). The comparison of CPU performance per power with SRAM-based, embedded DRAM and conventional STT-MRAM-based LLCs indicates that the presented novel nonvolatile LLC is the most suitable for large LLC.