Yoshiaki Asao

A 64Mb MRAM with clamped-reference and adequate-reference schemes

In order to realize a sub-Giga bit scale NVRAM, the novel MRAM based on the spin-transfer-torque (STT) switching has been intensively investigated due to its excellent scalability compared with a conventional magnetic field induce switching MRAM [1]. However, the memory cell size of STT-MRAM reported so far is still over 1µm2, and the memory capacity is limited to 32Mbit even in almost 100mm2 die size [2]. The large cell size is due to the large switching current of MRAM cells. In order to reduce the cell size, we have proposed the perpendicular tunnel magnetoresistance (P-TMR) device, and have confirmed its high potential to achieve lower switching current [3]. In this paper, a 64Mb STTMRAM with the P-TMR device having the circuit techniques to maximize operational margin is described.

Fault-tolerant designs for 256 Mb DRAM

This paper describes fault-tolerant designs, which have been used to boost the yield of a 286 mm/sup 2/ 256 Mb DRAM with x32 both-ends DQ. The 256 Mb DRAM consists of sixteen 16 Mb units, each containing one 128 Kb row redundancy block. This row redundancy block architecture allows flexible row redundancy replacement, where random faults, clustered faults, and grouped faults can be efficiently repaired. Flexible column redundancy replacement with interchangeable master DQs (MDQ) is used to allow a 256 b data compression without causing a data conflict, while improving the column access speed by 2 ns. A depletion NMOS bitline-precharge-current-limiter suppresses the current flow which occurs as a result of a wordline-bitline short-circuit to only 15 /spl mu/A per cross fail, avoiding a standby current fail. Consequently, the hardware results show a significant yield enhancement of 16 times relative to the intra-block/segment replacement. Detailed simulation results show that this 256 Mb DRAM allows 275 random faults to be repaired with 5.5% silicon area overhead for 80% chip yield.

Ion Beam Etching Technology for High-Density Spin Transfer Torque Magnetic Random Access Memory

A spin transfer torque magnetoresistive random access memory (STT-MRAM) is the most promising candidate for a non-volatile random access memory, because of its scalability, high-speed operation, and unlimited read/write endurance. An ion beam etching (IBE) is one of the promising etching methods for a magnetic tunnel junction (MTJ) of the STT-MRAM, because it has no after-corrosion and oxidation problems. In this work, we developed the multiple-step wafer-tilted IBE using computer calculation. Using optimized multiple-step IBE conditions, we fabricated MTJs without barrier-short defects.

Flexible test mode approach for 256-Mb DRAM

This paper describes a flexible test mode approach developed for a 256-Mb dynamic random access memory (DRAM). Test mode flexibility is achieved by breaking down complicated test mode control into more than one primitive test mode. The primitive test modes can be selected together through a WE CAS Before RAS (WCBR) cycle with a series of addresses for mode select. Although each primitive test mode may not complete a meaningful task alone, their combination performs many complex and powerful test modes. In this design, 64 primitive test modes are available. These can be combined to realize more than 19000 useful test modes. A new signal margin test mode is introduced which allows an accurate signal margin test even for small capacitance cells, which are difficult to identify in existing plate-bump method. A flexible multiwordline select test mode effectively performs a toggled wordline disturb test, a long t/sub RAS/ wordline disturb test, and a transfer gate stress voltage test, without causing any unnatural array disturbance. Finally, test modes, which can directly control the timing of sense amplifiers and column select lines, are discussed.

Reduction of switching current distribution in spin transfer magnetic random access memories

In this paper, the switching current distribution by spin transfer torque is investigated for CoFeB∕MgO∕CoFeB magnetic tunnel junctions (MTJs). The distribution of the spin transfer switching current for a MTJ with junction size of 85×110nm2 is 16% when the duration of applied pulse current is 5ms. In the case of magnetization reversal with magnetic field induced by current with 5ms pulse duration, the distribution of the switching field is 8.3%. According to our micromagnetic simulation, it is found that the spin transfer current switching seems to exhibit a nonuniform magnetization reversal process, whereas the magnetization switching by the magnetic field exhibits a uniform magnetization reversal process. This leads to the broader distribution related to the repeatability.In this paper, the switching current distribution by spin transfer torque is investigated for CoFeB∕MgO∕CoFeB magnetic tunnel junctions (MTJs). The distribution of the spin transfer switching current for a MTJ with junction size of 85×110nm2 is 16% when the duration of applied pulse current is 5ms. In the case of magnetization reversal with magnetic field induced by current with 5ms pulse duration, the distribution of the switching field is 8.3%. According to our micromagnetic simulation, it is found that the spin transfer current switching seems to exhibit a nonuniform magnetization reversal process, whereas the magnetization switching by the magnetic field exhibits a uniform magnetization reversal process. This leads to the broader distribution related to the repeatability.

Improvement of robustness against write disturbance by novel cell design for high density MRAM

A new bit cell designed to have an excellent astroid is presented from the viewpoints of both theory and experiment. The switching mechanism is unique. The robustness against the disturbance of half-selected bits is improved. Its excellent astroid improves thermal stability and has the potential to achieve extremely high density magnetoresistive random access memory (MRAM).

A 17-ns 4-Mb CMOS DRAM

A 17-ns nonaddress-multiplexed 4-Mb dynamic RAM (DRAM) fabricated with a pure CMOS process is described. The speed limitations of the conventional DRAM sensing technique are discussed, and the advantages of using the direct bit-line sensing technique are explained. A direct bit-line sensing technique with a two-stage amplifier is described. One readout amplifier is composed of a two-stage current-mirror amplifier and a selected readout amplifier is activated by a column decoder output before the selected word line rises. The amplifier then detects a small bit-line signal appearing on a bit-line pair immediately after the word-line rise. This two-stage amplification scheme is essential to improving access time, especially in the case of a CMOS process. The high sensitivity of the readout amplifier is discussed, and the electrical features and characteristics of the fabricated DRAM are reported. >

Bit yield improvement by precise control of stray fields from SAF pinned layers for high-density MRAMs

A write-operating window with a 100% functional bit yield was successfully obtained by the control of stray fields from synthetic antiferromagnetic (SAF) pinned layers in conventional magnetic random access memories with rectangular magnetic tunneling junction bits. The stray fields were controlled by a newly developed ion-beam etching technique without causing damage and by a precise setting of the SAF pinned layer thickness, and are balanced with Neel coupling fields. As a result, it was found that symmetric switching astroid curves with no offset were obtained and switching distributions were minimized at the zero offset field.

Design and process integration for high-density, high-speed, and low-power 6F/sup 2/ cross point MRAM cell

A cross point (CP) cell with hierarchical bit line architecture was proposed for magnetoresistive random access memory (MRAM) based in Y. Shimizu et al. (2004). The new CP cell has a potential high density of 6F/sup 2/ and a faster access time than the conventional CP cell. A cell layout design to realize 6F is proposed and associated issues are resolved. Further, a 1Mb MRAM chip based on this structure has been fabricated utilizing 0.13 /spl mu/m CMOS technology and 0.24/spl times/0.48 /spl mu/m/sup 2/ magnetic tunnel junction (MTJ) sandwiched with the most efficient yoke wires ever reported. The access time of 250 ns and 1.5 V operations are successfully demonstrated with the integrated 1Mb chip.

Ion-Beam-Etched Profile Control of MTJ Cells for Improving the Switching Characteristics of High-Density MRAM

The effect of the reduction of the sidewall redeposition layer of magnetic materials is investigated for submicron-patterned magnetic random access memory (MRAM) cells. The sidewall redeposition layer is made at the first etch step of a magnetic tunnel junction (MTJ) with ion beam etching (IBE) in the case that the sidewall angle of a hard mask is steep. By controlling the etched profile at the time of the first IBE step, formation of the redeposition layer is prevented. Functional test results of 1-Kb MRAM arrays show that the sidewall redeposition layer enlarges fluctuation of switching current, and reduces the write operation region. The effect of the sidewall redeposition on the switching characteristics of MRAM arrays is explained qualitatively by micromagnetic simulation solving the Landau-Lifshitz-Gilbert (LLG) equation