Naohiko Irie

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs

Hierarchical power distribution with a power tree has been developed. The key features are a power-tree structure with three power-tree management rules and a distributed common power domain implementation. The hierarchical power distribution supports a fine-grained power gating with dozens of power domains, which is analogous to a fine-grained clock gating. Leakage currents of a 1 000 000-gate power domain were effectively reduced to 1/4000 in multi-CPU SoCs with minimal area overhead

A resume-standby application processor for 3G cellular phones

A 389MIPS application processor for 3G cellular phones is implemented in a 0.13/spl mu/m dual-V, process. This dual-issue superscalar CPU with DSP runs at 216MHz at 1.2V and provides a resume-standby mode with a quick recovery feature using data retention of memory. The leakage current is estimated to be 98/spl mu/A when the power supply is internally cut off.

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM

This paper presents a three-dimensional (3D) system integration of a commercial processor and a memory by using inductive coupling. A 90nm CMOS 8-core processor, back-grinded to a thickness of 50µm, is mounted face down on a package by C4 bump. A 65nm CMOS 1MB SRAM of the same thickness is glued on it face up, and the power is provided by conventional wire-bonding. The two chips under different supply voltages are AC-coupled by inductive coupling that provides a 19.2Gb/s data link. Measured power and area efficiency of the link is 1pJ/b and 0.15mm2/Gbps, which is 1/30 and 1/3 in comparison with the conventional DDR2 interface respectively [1]. The power efficiency is improved by narrowing a transmission data pulse to 180ps. Reduced timing margin for sampling the narrow pulse, on the other hand, is compensated against timing skews due to layout and PVT variations by a proposed 2-step timing adjustment using an SRAM through mode. All the bits of the SRAM is successfully accessed with no bit error under changes of supply voltages (±5%) and temperature (25°C, 55°C).

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption

A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm2 die achieves a floating-point performance of 16.8GFLOPS

3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link

This paper describes a three-dimensional (3-D) system integration of a full-fledged processor chip and two memory chips using inductive coupling. To attain a 3-D communication link with a smaller area and lower power-consumption, shortening the link distance and preventing signal degradation due to unused inductors are important challenges. Therefore, we developed a new 3D-integrated wire-penetrated multi-layer structure for a shorter link distance and an open-skipped-inductor scheme for suppressing signal degradation. In addition, to avoid undefined-value propagation in stacking multi-memories using an inductive-coupling link, we proposed a memory-access-control scheme with a pinpoint-data-capture scheme. We demonstrate that three fabricated chips can be successfully AC-coupled using inductive coupling. The power and area efficiency of the link are 1 pj/b and 0.15 mm2 /Gbps, respectively, which are the same as those of two-chip integration.

Interference from power/signal lines and to SRAM circuits in 65nm CMOS inductive-coupling link

This paper discusses interference of an inductive-coupling link in 65nm CMOS. Electromagnetic interference from power/signal lines and to SRAM was simulated and measured. Interference from power lines for mobile applications (line and space) is smaller than that for high-performance applications (mesh type). Interference from signal lines requires only 9% of additional transmit power even in the worst case of logic circuits. In typical operation range, interference to SRAM is ignorable. Only when supply voltage is much lower than typical range, the bit-line noise from the inductive-coupling link influences SRAM operation. Interference to SRAM is small compared with other influences such as device variations and soft errors.

Domain Partitioning Technology for Embedded Multicore Processors

Todays embedded systems require both real-time control functions and IT functions. Integrating multiple operating systems on a multicore processor is one way to meet these requirements. However, in this approach, one operating systems failure can bring down the other operating systems. To address this issue, the authors propose a multidomain embedded system architecture with a physical partitioning controller.

Embedded SoC Resource Manager to Control Temperature and Data Bandwidth

A 0.4mm2 SoC resource manager controls operating frequency and allocates data bandwidth using various monitored information such as temperature, frequency of IP blocks and number of operations executed. Results show an increase of allowable temperature range by 30degC for real-time operations of two processor cores and two media processing cores. The design is fabricated in an 8M 90nm CMOS process

A 133 MHz 170 mW 10 /spl mu/A standby application processor for 3G cellular phones

An application processor for 3G cellular phones, using 0.18 /spl mu/m CMOS technology, includes a single CPU and DSP core with an on-chip 128 kB SRAM. It enables software-based 15 frames/s MPEG-4 encoding of QCIF Simple @L1 at 70 MHz and 140 mW. Standby current of the processor is <10 /spl mu/A in a partially powered standby mode using separate power lines.

Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration

Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions.