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Featured researches published by Naohiro Kiyota.


IEEE Micro | 2015

Sparc64 XIfx: Fujitsu's Next-Generation Processor for High-Performance Computing

Toshio Yoshida; Mikio Hondou; Takekazu Tabata; Ryuji Kan; Naohiro Kiyota; Hiroyuki Kojima; Koji Hosoe; Hiroshi Okano

Sparc64 XIfx, the latest high-performance computing processor, includes a 34-core processor and achieves 1.1 teraflops of peak performance. This chip is designed for massive parallel supercomputer systems that realize high performance for a wide range of real applications. As groundwork for exascale supercomputing, it has made major technological changes from the previous Sparc64 processor in the instruction set architecture, microarchitecture, memory modules, and embedded interconnect.


Archive | 2004

Multithread processor and thread switching control method

Toshio Yoshida; Masaki Ukai; Naohiro Kiyota


Archive | 2007

Cache control device and control method

Naohiro Kiyota


IEEE Micro | 2013

Sparc64 X: Fujitsu's New-Generation 16-Core Processor for Unix Servers

Toshio Yoshida; Takumi Maruyama; Yasunobu Akizuki; Ryuji Kan; Naohiro Kiyota; Kiyoshi Ikenishi; Shigeki Itou; Tomoyuki Watahiki; Hiroshi Okano


Archive | 2005

Multithread controller and control method

Naohiro Kiyota; Iwao Yamazaki


Archive | 2009

Cache memory apparatus, execution processing apparatus and control method thereof

Hiroyuki Imai; Naohiro Kiyota; Tsuyoshi Motokurumada


Archive | 2006

Multiprocessor system, processor, and cache control method

Naohiro Kiyota


Archive | 2007

Cache memory device, arithmetic processing unit, and its control method

Hiroyuki Imai; Naohiro Kiyota; Tsuyoshi Motokurumada


Archive | 2006

Cache memory device and cache memory control method

Takashi Miura; Naohiro Kiyota


Archive | 2011

INFORMATION PROCESSING DEVICE AND CACHE MEMORY CONTROL DEVICE

Naohiro Kiyota

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