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Dive into the research topics where Ryuji Kan is active.

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Featured researches published by Ryuji Kan.


international symposium on microarchitecture | 2010

Sparc64 VIIIfx: A New-Generation Octocore Processor for Petascale Computing

Takumi Maruyama; Toshio Yoshida; Ryuji Kan; Iwao Yamazaki; Shuji Yamamura; Noriyuki Takahashi; Mikio Hondou; Hiroshi Okano

The Sparc64 VIIIfx eight-core processor, developed for use in petascale computing systems, runs at speeds of up to 2 GHz and achieves a peak performance of 128 gigaflops while consuming as little as 58 watts of power. Sparc64 VIIIfx realizes a six-fold improvement in performance per watt over previous generation Sparc64 processors.


symposium on vlsi circuits | 2010

Fine grained power analysis and low-power techniques of a 128GFLOPS/58W SPARC64 ™ VIIIfx processor for peta-scale computing

Hiroshi Okano; Yukihito Kawabe; Ryuji Kan; Toshio Yoshida; Iwao Yamazaki; Hitoshi Sakurai; Mikio Hondou; Nobuyuki Matsui; Hideo Yamashita; Tatsumi Nakada; Takumi Maruyama; Takeo Asakawa

An 8-core SPARC64™ VIIIfx processor is fabricated in a 45nm CMOS process and achieves a peak performance of 128GFLOPS. Measured results show that the processor consumes only 58W of power when executing a maximum power program. Fine-grained power analysis was used to tune the micro-architecture for low power consumption, and circuit-level low-power techniques were developed. Water cooling and supply voltage adjustment contribute to power reduction at the system level.


IEEE Micro | 2015

Sparc64 XIfx: Fujitsu's Next-Generation Processor for High-Performance Computing

Toshio Yoshida; Mikio Hondou; Takekazu Tabata; Ryuji Kan; Naohiro Kiyota; Hiroyuki Kojima; Koji Hosoe; Hiroshi Okano

Sparc64 XIfx, the latest high-performance computing processor, includes a 34-core processor and achieves 1.1 teraflops of peak performance. This chip is designed for massive parallel supercomputer systems that realize high performance for a wide range of real applications. As groundwork for exascale supercomputing, it has made major technological changes from the previous Sparc64 processor in the instruction set architecture, microarchitecture, memory modules, and embedded interconnect.


Archive | 1988

ARITHMETIC PROCESSING UNIT

Ryuji Kan; Tomohiro Tanaka; Toshio Yoshida


IEEE Micro | 2013

Sparc64 X: Fujitsu's New-Generation 16-Core Processor for Unix Servers

Toshio Yoshida; Takumi Maruyama; Yasunobu Akizuki; Ryuji Kan; Naohiro Kiyota; Kiyoshi Ikenishi; Shigeki Itou; Tomoyuki Watahiki; Hiroshi Okano


Archive | 2008

OPERATION VERIFICATION METHOD FOR VERIFYING OPERATIONS OF A PROCESSOR

Hideo Yamashita; Ryuji Kan


Archive | 2008

Processing apparatus and control method thereof

Mikio Hondou; Ryuji Kan; Toshio Yoshida


Archive | 2006

Arithmetic operation apparatus, information processing apparatus and register file control method

Ryuji Kan; Hideo Yamashita; Toshio Yoshida


Archive | 2006

Register window system and method that stores the next register window in a temporary buffer

Ryuji Kan; Hideo Yamashita; Toshio Yoshida


Archive | 2014

Arithmetic processing device, information processing device, control method for information processing device, and control program for information processing device

Shuji Yamamura; Masaharu Maruyama; Toshio Yoshida; Ryuji Kan; Naohiro Kiyota; Mikio Hondo; Tsuyoshi Motokurumada

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