Naoki Kato

LADIES: an automatic layout system for analog LSI's

The authors have developed a prototype system for analog LSI layout design which ensures the functionality of circuits. The procedural initial layout program is based on a clustering algorithm and a river routing algorithm and it manipulates mathematically specified layout constraints. Before and after this program the system uses a knowledge base to manipulate complex conditions and thereby avoid circuit malfunction. Using circuit descriptions and knowledge about layout constraints as related to the circuits, a preprocessing program generates specific layout constraints which ensure the functionality of circuits. A postprocessing program eliminates unused space, taking the various constraints into account. The authors have also developed a predictive inference mechanism which selects suitable actions to get better results. In an experiment involving a 71-element block, the authors obtained a layout which follows all constraints and is only 8% larger than the manual layout.<<ETX>>

1 kW portable fuel cell system based on PEFCs

We have developed a 1 kW portable fuel cell system that is powered by polymer electrolyte fuel cells (PEFCs). It consists of a cabinet that contains a fuel cell stack, hydrogen gas cylinders, an inverter, a control unit, and other components. The volume and mass of the system are about 275 l and 120 kg. The system can supply 1 kW of AC 100 V power for three hours using two 10 l hydrogen gas cylinders. The warm-up time is only about one minute. The system generates electric power from the reaction between hydrogen and oxygen in air, so it is very quiet and does not emit harmful gases or carbon dioxide. Our portable fuel cell system has been applied as a long-term power back-up system in combination with an uninterruptible power supply (UPS) and a synchronization-switch system.

A layout improvement method based on constraint propagation for analog LSI's

proposes a flexible layout improvement LSIs based on constraint urouagation. The - _method performs rerouting and compaction for a given initial layout pattern by considering design rules and layout constraints. First, it extracts topological relationship between cells and routing wires. Then, it makes a constraint graph according to design rules and various layout constraints which ensure circuit functionality. This algorithm modifies the layout by propagating constraints on the graph according to layout improvement rule requirements. The algorithm enables layout modification while routing and ensures 100% routing like a channel router. It can also be used as a twodimensional compactor.We extended the line expansion algorithm for multi-layer routing. We implemented the basic features of the layout improvement method and tested them. Experimental results show that the proposed method rout 3/4 of the unconnected wires with a 16% area increase. Better performance is expected with full implementation.

RTL morphing: making IP-reuse work in system-on-a-chip designs

The proposed RTL morphing enables true IP-reuse design through flexible control of the RTL structure under the changes in performance requirements or delay constraints. This flexible RTL restructuring is provided by a new path-depth controlling method, which can optimize the depth of any path by changing the if-then-else nesting order of a basic logic unit (called a decision unit). The use of RTL morphing reduces the design period of a time-to-market pressured SoC of 4M transistors by two months with 18% operating frequency improvement.

Characteristics of arc-reducing effect by capacitor in commutation circuit

DC motors are indispensable to improve the automotive functions. Recently, 70-100 motors are installed on luxury cars and this number is increasing year by year. With the recent demand for improved fuel economy and better equipment layout, the improvement of the motors efficiency and the minimization of the motor size are the key to enhancing the competitive edge of the products. Adopting the high-density coil is an effective method for that, but it is accompanied by the commutation inductance rise which causes the commutation arc increase. The increase of commutation arc decreases motor life, because it causes the rise of brush/commutator wear. This report describes an arc-reducing effect obtained when capacitors are built into a commutation circuit for the purpose of reducing arcing under high commutation inductance conditions. The results of an evaluation using a equivalent commutation circuit and carbon brush/carbon flat-commutator showed that although a commutation circuit with built-in capacitor generated the same arc energy as a commutation circuit without a capacitor above a certain value of residual current, it displayed an excellent arc-reducing effect below that value of residual current.

Constant-ratio-coupled multi-grain digital synchronizer with flexible input-output delay selection for versatility in low-power applications

The constant-ratio-coupled multi-grain digital synchronizer (CRC-MGsynchronizer) is proposed as a means for making high-speed connections with very low power consumption, both among multiple chips such as processors, controllers, and storage devices, and among on-chip modules. The synchronizer not only provides a wide range of operating frequencies, but is fast locking and only occupies a small area on chip. Therefore, it contributes to large reductions in power consumption and costs. It is suitable for use in various low-power systems (e.g., battery-hungry mobile appliances and low-cost consumer electronic products). Three major techniques were applied to the design: 1)a multi-grain structure for the delay elements, which greatly reduces the number of gates while facilitating locking in a very small number of clock cycles;2) constant-ratio-coupled (CRC) delay lines (measurement versus generation)for flexible selection of the input-output delay; and 3) a new lock stage decision circuit (LSDC) scheme, conferring excellent testability. Moreover,the architecture is all-digital, and thus it has high process portability. By applying these techniques to a DDR memory interface circuit for a mobile application processor fabricated in 130-nm technology, we were able to reduce power consumption by 42% and chip area by 65% compared with a conventional implementation. Furthermore, the novel design spans a frequency range covering 12 times the minimum frequency.

Practical methodology of post-layout gate sizing for 15% more power saving

This paper presents a practical methodology of post-layout gate sizing for power reduction. Wire capacitance presumed in logic synthesis typically contains excessive margin for better timing closure in layout design. Power waste due to this can be reduced by post-layout gate sizing based on information obtained by backannotation. In this paper, we discuss a theory of optimal gate sizing in a signal path with surplus timing. We also, propose a practical design methodology where standard cells are reselected from a cell library by the theory, replaced by engineering change order, and timing constraints are verified by a static timing analyzer. We have applied the methodology to a 700k-gate commercial application processor for 3G cellular phones. Even though the original design was optimized for 133MHz, 170mW operation in a 0.18μm CMOS technology, power dissipation was further squeezed by 15% in combinational logic without compromising the performance.

An Alternative Cyclic Synchronous Mirror Delay for Versatility in Highly Integrated SoC

We describe an alternative cyclic synchronous mirror delay (ACSMD) for highly integrated SoCs of mobile application processors. ACSMD provides the following advantages: wide operational frequency range from 0.5 to 400 MHz, 0.08 mm2 chip area, and 6.13 mW power consumption @ 400 MHz operation. The chip area and power consumption are reduced by 95% of those of a conventional hierarchical SMD with the same operational frequency and resolution. Key circuit technologies are cyclic delay line, alternating use of three delay lines, and a new loop counter.