Takeo Yamashita

Neuron-MOS multiple-valued memory technology for intelligent data processing

This paper presents RAM technology that quantizes analog input data and stores it as multi-valued data for intelligent data processing. Moreover, data association and classification according to the degree of association can also be performed at the memory-cell level without any software manipulation. The implementation of such intelligent functions by a memory cell has been facilitated by unique circuit configurations of the neuron MOS (vMOS) transistor, a multi-functional device that simulates the action of biological neurons. These concepts are experimentally verified by test devices fabricated by a standard double-polysilicon CMOS process. Although the circuits are explained for a 4-valued system, the designs can be extended to an 8-valued (or greater) system.<<ETX>>

Minimizing damage and contamination in RIE processes by extracted-plasma-parameter analysis

It is reported that important plasma parameters for reactive ion etching (RIE) processes, such as ion energy and ion flux density, can be extracted from a simple RF waveform analysis at the excitation electrode in a conventional cathode-coupled, parallel-plate plasma RIE system. This analysis does not introduce any contamination or disturbances to the process. By using the extracted plasma parameters, surface damage and contamination in Si substrates induced by reactive ion etching in a SiCl/sub 4/ plasma were investigated. Optimum RIE conditions were then confirmed by studying the relationship between these parameters and the etching performance. It is shown using the experimental data that low-energy high-flux etching is the direction for high performance RIE in future ULSI fabrication. >

Neuron-MOS Parallel Search Hardware for Real-Time Signal Processing

Circuit architecture for parallel data processing directly carried out on the hardware have been developed based on a high-functionality transistor, neuron MOSFET (neuMOS or νMOS for short). In the νMOS data sorting circuit, multiple analog input data are numbered in binary codes according to the order of their magnitudes after a single ramp voltage scan. A νMOS motion-vector detector has been developed for on-chip moving image processing based on x- and y-projection data. The circuit can find the movement of an image in two successive frames within a few 100 nsec. The projection-data-based motion detection algorithm has been tested by computer simulation. Test circuits were fabricated by a double-polysilicon CMOS process and basic operation of the circuits has been demonstrated.