Naoki Kumagai

A new IGBT with a monolithic over-current protection circuit

A new IGBT structure with a monolithic overcurrent sensing and protection circuit has been developed. The feature of this device is a novel integration of a sensing and protection circuit which consists of a sensing IGBT, lateral n-MOSFET, polycrystalline silicon diode and resistor with an IGBT structure. The conventional IGBT fabrication process is available to this device with only one more photomask. Comparison of not only a short circuit safe operating area but both a trade-off characteristics between an on-state voltage drop and a turn-off loss and reverse biased safe operating area with a conventional IGBT has been investigated. Since exhibiting a large short circuit safe operating area without deterioration of any other device characteristics, this device can be applied to not only a soft switching application like voltage resonant circuit but a hard switching application like snubberless inductive load circuit.

The IGBT with monolithic overvoltage protection circuit

A novel IGBT (insulated-gate bipolar transistor) with a monolithic overvoltage protection circuit has been developed to obtain high resistance to overvoltage stress. This device is characterized by novel integration of an avalanche diode with an IGBT structure. The conventional IGBT process can be used to fabricate this device without any additional photomasks. Since it exhibits a large safe operating area, this device can be applied not only to a soft switching application like a voltage resonant circuit but also to a hard switching application like a snubberless inductive load circuit.<<ETX>>

Analysis of IPM current oscillation under short circuit condition

It is observed that the collector current in an IGBT oscillates under short circuit conditions. In particular, severe oscillation occurs when the IGBT is connected to a current limiting circuit. This current oscillation has some undesirable effects on application circuits using IGBTs or IPMs (intelligent power modules). We have revealed the current oscillation mechanism by means of experiments and simulation. From the results, the IGBT cell structure itself triggers oscillation of the gate voltage and collector current. The parasitic inductance existing in the module and the current limiting circuit connected to the IGBT have an additional influence on the current oscillation behaviour. Current oscillation can be damped successfully by adjusting the parasitic inductance or improving the properties of the current limiting circuit.

Self-shielding: new high-voltage inter-connection technique for HVICs

A new, cost-effective, high-voltage inter-connection technique for HVICs, named Self-Shielding, is proposed. To avoid the lowering of breakdown voltage of high-voltage devices affected by the electric potential of overlying interconnections, self-shielding technique utilizes only the native PN-junction structures of high-voltage devices themselves. No additional shielding structure is required even to realize a very high-voltage IC above 1000 V. Design concept and device structures are presented together with the experimental results on the operation of self-shielded 1200 V level-shifters.

Low V f and highly reliable 16 kV ultrahigh voltage SiC flip-type n-channel implantation and epitaxial IGBT

Flip-type n-channel implantation and epitaxial (IE)-IGBT on 4H-SiC carbon face with an epitaxial p++ collector layer was investigated. In this study, we employed the IEMOSFET as a MOSFET structure with original wet gate oxidation method, to realize high channel mobility. We were able to achieve an ultrahigh blocking voltage of more than 16 kV, extremely low forward voltage drop of 5 V at 100 A/cm2 and small threshold voltage shift (<; 0.1 V). These characteristics are useful for Smart Grid and HVDC systems, the use of which would realize a low carbon emission society.

Switching loss analysis of shorted drain non punch-through and punch-through type IGBTs in voltage resonant circuit

The dissipated turn-off losses of shorted drain non-punch-through and punch-through type IGBTs (insulated-gate bipolar transistors) are investigated for voltage resonant circuit application. These characteristics are analyzed experimentally and calculated by using a two-dimensional device simulator. It is shown that the shorted drain structure is not effective for decreasing the dissipated loss, whereas the optimized punch-through type IGBT is suitable for this circuit application.<<ETX>>

Device Performance and Switching Characteristics of 16 kV Ultrahigh-Voltage SiC Flip-Type n-Channel IE-IGBTs

Ultrahigh-voltage SiC flip-type n-channel implantation and epitaxial (IE)-IGBTs were developed, and the static and dynamic performance was investigated. A large device (8 mm × 8mm) with a blocking voltage greater than 16 kV was achieved, and an on-state current of 20 A was obtained at the low on-state voltage (Von) of 4.8 V. RonAdiff was 23 mΩ·cm2 at Von = 4.8 V. In order to evaluate the switching characteristics of the IE-IGBT, ultrahigh-voltage power modules were assembled. A chopper circuit configuration was used to evaluate the switching characteristics of the IE-IGBT. Smooth turn-off waveforms were successfully obtained at VCE = 6.5 kV and ICE = 60 A in the temperature range from room temperature to 250°C.

Experimental and Numerical Studies on

Experimental results on the high-voltage level shifter and dV/dt robustness of 1200 V high voltage integrated circuits (HVICs) using a self-isolation (SI) structure are reported for the first time. Generally, because high dV/dt stress is applied to HVICs during insulated gate bipolar transistor (IGBT) switching, significant displacement current flows through a high-voltage isolation capacitance. This current acts as the base current of parasitic pnp and npn transistors, and causes a potential drop in their base region. In the worst case, this parasitic operation causes device destruction. In this study, not only the normal operation of HVICs but suppression of the parasitic transistors under high dV/dt condition are experimentally demonstrated by considering a high-side layout design and back diverter electrode.

dV/dt

Photo-induced ESR and its annealing behavior in melt-quenched GeSx (x=1.5, 0.8 and 2) glasses have been studied. Measurement of the effect of gamma-ray irradiation on the photo-induced ESR reveals the important role of quenched-in dangling bonds in the photo-enhancement of the ESR signal. The isothermal and isochronal annealing behavior of the photo-induced ESR in GeSx (x=1.5, 1.8 and 2) glasses can be explained in terms of a first-order reaction in which a Gaussian distribution of the activation energy is assumed.

Robustness of 1200 V High-Voltage Integrated Circuits Using Self-Isolation Structure

We have investigated the gate current–voltage (I g–V g) characteristics of n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) and p-MOS capacitors on the 4H-SiC face. The gate current response to a change in gate voltage has a very slow part, which has been considered to be due to slow traps in the oxide near the SiO2–SiC interface. However, we found that the slow response can be explained by fast interface traps if the traps have a relatively large concentration. Carrier injection into the interface traps results in a change in the surface potential, and this suppresses the further injection of carriers. This new model can explain many electrical properties such as the constant-current behavior in the I g–V g characteristics, which was confirmed by one-dimensional (1D) device simulation. According to this model, the interface traps will not be occupied up to the surface Fermi level within the general time scale of the measurement. In spite of the arguments described above, slow traps also probably exist near the interface between SiO2 and SiC.