Naoki Tamaoki

Simulation of arsenic in situ doping with polysilicon CVD and its application to high aspect ratio trenches

Filling high aspect ratio trenches is an essential manufacturing step for state of the art memory cells. Understanding and simulating the transport and surface processes enables one to achieve voidless filling of deep trenches, to predict the resulting profiles, and thus to optimize the process parameters and the resulting memory cells. Experiments on arsenic doped polysilicon deposition show that under certain process conditions step coverages greater than unity can be achieved. We developed a new model for the simulation of arsenic doped polysilicon deposition, which takes into account surface coverage dependent sticking coefficients and surface coverage dependent arsenic incorporation and desorption rates. The additional introduction of Langmuir-Hinshelwood type time dependent surface coverage enabled the reproduction of the bottom up filling of the trenches in simulations. Additionally, the rigorous treatment of the time dependent surface coverage allows to trace the in situ doping of the deposited film. The model presented was implemented and simulations were carried out for different process parameters. Very good agreement with experimental data was achieved with theoretically deduced parameters. Simulation results are shown and discussed for polysilicon deposition into 0.1 /spl mu/m wide and 7 /spl mu/m deep, high aspect ratio trenches.

Monitoring Arsenic In-Situ Doping with Advanced Models for Poly-Silicon CVD

Experiments of As-doped poly-silicon deposition have shown that under certain process conditions step coverages > 1 can be achieved. We have developed a new model for the simulation of As-doped poly-silicon deposition, which takes into account surface coverage dependent sticking coefficients and surface coverage dependent As incorporation and desorption rates. The additional introduction of Langmuir type time-dependent surface coverage enabled the reproduction of the bottom-up filling of the trenches. In addition the rigorous treatment of the time-dependent surface coverage allows to trace the in-situ doping of the deposited film. Simulation results are shown for poly-Si deposition into 0.1 μm wide and 7 μm deep, high aspect ratio trenches.

High-Speed Rotating-Disk Chemical Vapor Deposition Process for In-Situ Arsenic-Doped Polycrystalline Silicon Films

We have developed high-speed rotating-disk chemical vapor deposition (CVD) equipment for polycrystalline silicon (poly-Si) films. This CVD equipment has an enhanced ability to reduce the boundary layer thickness at a given temperature above a wafer surface, and to suppress vapor-phase reactions. We investigated in-situ arsenic-doped poly-Si film deposition using silane (SiH4), arsine (AsH3) and nitrogen (N2) in a high-speed rotating-disk CVD as functions of AsH3 flow rate and deposition temperature. Both the deposition rate and resistivity decreased with increasing AsH3 flow rate. A deposition rate of 120 nm/min, a resistivity of 16 mΩcm, a film thickness nonuniformity of ±5%, and a number of particles of less than 20 (over 200 nm in diameter) were achieved at a deposition temperature of 680°C for in-situ arsenic-doped poly-Si deposition on a 200-mm-diameter silicon (Si) wafer. Moreover, it was confirmed that the concentration of As in the poly-Si film was low at the initial stage of deposition, and that this process has a high gap filling capability in a hole of 0.18 µm width and 7 µm depth. It was also confirmed that there were conditions for a high step coverage of more than 1. These properties are inferred to be due to the adsorbed AsH3 preventing the adsorption of SiH4.

Topography simulation of BiCS memory hole etching modeled by elementary experiments of SiO 2 and Si etching

A topography simulation of BiCS memory hole etching is performed. The model parameters are fitted by elementary experiments of Si and SiO2 etching, and BiCS topography simulation is performed without parameter fitting. Our new model describes the experimental topography of BiCS memory hole, including taper angles and undercuts of stacked films. The point of the modeling is that it takes into consideration removal of O-oriented deposition films by reflected ions from tapered SiO2 sidewall.

Modeling of Deposition During C5F8/CO/O2/Ar Plasma Etching Using Topography and Composition Simulation

We proposed a simple model to simulate topography and composition of deposited films. Our model described topography and composition of deposited fluorocarbon films in C5F8/CO/O2/Ar plasma etching. Analysis of compositions facilitated making of the reactor and surface models, and our model could treat the gas flow and open width dependency of the SiO2 etching. It was very useful in designing devices for easy manufacturing.

Acceleration of CVD Step Coverage Simulation Applied to DSMC Method.

This paper describes acceleration of the numerical simulation for chemical vapor deposition (CVD) step coverage problems. The CVD process is used to deposit thin films during LSI production. The thin film deposition process is generally simulated using a combination of the direct simulation Monte Carlo (DSMC) method and trench profile evolution, but much time is required to compute a trench filling shape when sticking probability is small. In the present work, reduction of the computation time was achieved by parallel processing using an engineering workstation (EWS) network system and stick-at-all-the-reflection-points (SARP) method which was newly developed. In the former case, more than 85% parallel efficiency on a 20-EWS system was achieved. In the latter case, computation was more than 780000 times faster than by the conventional method when an experimental poly-Si deposition process was considered.

Simulation of CVD Step Coverage for SiH4 using Parallel Processing of DSMC Method

This paper describes the basic study of the simulation of chemical vapor deposition (CVD) step coverage that is used to estimate the deposition of thin films in LSI production. Given the trend toward extremely high density in the semiconductor manufacturing process, such as that of LSIs, the deposition process of silicon thin film on the circuit pattern needs to be accurate. To optimize the deposition of thin film around the trench of the order of less than a micron, computer simulations of the step coverage and of the film growth rate in the process are very important. In this simulation reported in this paper, the thin film deposition process, whose reaction is modeled as silicon from silane (SiH4) and silylene (SiH2), is solved using the direct simulation Monte Carlo (DSMC) method. The DSMC method is usually adopted in this case, but, since 1) this method solves the Boltzmann equation with a huge amount of molecular collisions and free motions and 2) sticking probability of molecules is of the order of 10-5 [1], even a high performance computer needs much time for this calculation. Although the performance of supercomputers and other types of computers is improving, the DSMC method as conventionally applied seems to be reaching its limit in terms of practicality.