Naoko Kuwahara

Primary evaluation of proximity and resist heating effects observed in high-acceleration voltage e-beam writing for 180-nm-and-beyond rule reticle fabrication

Higher resolution and accuracy are required in e-beam lithography for reticle fabrication for coping with further advances in optical lithography. The trend is to use high acceleration voltage (50 kV) e-beam to improve spatial resolution. However, in the case of high acceleration e-beam writing, a drastic critical dimension (CD) change is caused by a strong proximity effect and a large resist heating effect. The proximity effect is caused by the increase in the back- scattering radius. The back-scattering radius was estimated by two independent observations of the CD variation of a monitor and the thickness variation of a partially developed resist. It is found to be ca. 15 nm. Using the shot time modulation as a proximity correction reduced the proximity effect to a small level: CD error due to the pattern density change remained within 10 nm. On the other hand, the resist heating effect is caused by the change in resist dissolution speed by the temperature rise of the resist. In reducing this effect, multi-pass writing is found to be effective. The range of the CD error of 2 micrometer lines-and-spaces in the writing field has been reduced from 22 nm to 6 nm by changing the writing from one pass to four passes for a conventional resist. Moreover, when a chemically amplified resist (CAR) is exposed through one-pass writing, the range of the CD error is found to be 8 nm. Therefore, the use of the CAR is effective in reducing the resist heating effect. Simulation software ProBEAM/3D and TEMPTATION were used to obtain three- dimensional resist profile and the transient temperature rise of the resist, respectively. Both provided results that agreed well with those by experiment.

Imaging quality analysis using direct Monte Carlo simulation and CAR reaction model in mask fabrication

We have developed a novel EB lithography simulator, which can analyze imaging quality such as Line Edge Roughness (LER), pattern distortion, and corner rounding for the mask fabrication process. The simulator has a direct Monte Carlo calculation mode with unequal mesh dividing, works on cluster PCs hardware, and installs an exact Chemically Amplification Resist (CAR) reaction model. The simulation analysis line and contact hole patterns clarify that intrinsic LER induced by electron scattering is dependent on the exposure dose below 10uC/cm2 and has strong dependence on diffusion length. Moreover, the simulation identify that there is an optimum point around 10uC/cm2 of sensitivity and 30nm of diffusion length, considering corner rounding effect. The developed simulator demonstrates that direct Monte Carlo simulation can analyze the imaging quality of mask pattern quantitatively and practically, and has the potential to be a mainstream for EB lithography simulation.

Hybrid EB-writing technique with a 50 kV-VSB writer and a 100 kV-SB writer for nanoimprint mold fabrication

Nanoimprint lithography is a candidate for lithography for the hp32nm and hp22nm nodes. Molds or templates for it are being developed on the basis of the process of making phase-shift photomasks. The combination of a 50 kV-VSB (variable shaped beam) EB writer and a chemically amplified resist (CAR) does not have a resolution sufficient for 1X patterning. On the other hand, a combination of a 100 kV-SB (spot beam) EB writer and a non-CAR satisfies the resolution requirement, but this combination leads to an extremely low throughput due to low resist sensitivity. To increase the throughput, we have examined double patterning and double exposure with hybrid use of two different types of writers, a 50 kV-VSB writer, JBX-9000MV, for delineating fine features and a 100 kV-SB writer, JBX-9300FS, for delineating rough features. Overlay accuracy is a key item in such hybrid writing. The results of an overlay accuracy evaluation together with a throughput improvement will be reported in this paper. An estimation of the time for writing a gate layer has given a good example; the writing time for hybrid writing is reduced to about half of the time for 100kV-SB writing. The overlay accuracy for double patterning is found to be 20nm (3σ). However, we are confident that we will be able obtain an overlay accuracy of 10nm (3σ) by improving the image placement accuracy of the JBX-9300FS. An example of double exposure is also shown.

Image placement accuracy of single-membrane stencil masks for e-beam lithography

Three stencil masks with simple die layouts on 24 mm x 24 mm Si membranes are made to compare simulation and experiment on image placement (IP). A pseudo finite element (FE) modeling is adopted. Displacements predicted by simulation are found to be smaller than experimental values, but both agree qualitatively. Four stencil masks with die layouts that model on ULSI hole layers in 30% opening ratio and pattern arrangement are successfully made. Displacements are reduced to 1/4 by adopting IP correction. The IP correction of EB data is found to be a useful method of reducing IP error.

Experimental analysis of image placement accuracy of single-membrane masks for LEEPL

We have fabricated seven masks with different patterns on a 27 mm x 34 mm single-membrane for Low Energy Electron-beam Proximity Lithography (LEEPL) by the wafer-flow process. We have examined the membrane flatness and image placement (IP) accuracy, which are essential qualities to be assured. We summarize the results as follows: Masks with membranes of 13 MP and 20MPa stress satisfy the membrane flatness requirement of less than 2 μm while a mask with a 6 MPa membrane does not. Maps of the distortion induced by the wafer-flow process are obtained for the masks with 13 MPa and 20 MPa membranes and their performance is explained in terms of the contraction of the mask substrate. The out-of-plane distortion for a 3 mm x 3 mm block of dense hole patterns with an opening ratio, ranging from 10% to 40%, has been evaluated. The distortion induced by the block has been evaluated and the effect of the local magnification correction on the IP error is examined. Maps of the distortion induced by the wafer-flow process and 4 x 4 blocks of 10% and 20% opening are obtained for a mask with 13 MPa membrane and the distortion induced by the blocks is estimated in 3σ. The uncorrectable IP error for the mask with the blocks of 10% opening is estimated to be 10 nm (in 3σ), which satisfies the specification for LEEPL masks.

PEC-fogging effect analysis using high-performance EB simulator capable of large area mask pattern simulation

We have developed a novel EB lithography simulator, which can analyze pattern profiles and CDs for an unlimited area. The simulator has a parallel Monte Carlo calculation mode with unequal mesh dividing, works on PC cluster hardware, and the new convolution algorithm. The simulation pattern profiles well-reproduced, observable chemically amplified resist pattern profiles. Simulated CD errors also well agree with measured PEC errors, when we compare the CDs for isolated line, line in lines/spaces and isolated space. Finally, the simulator also predicts the CD error difference between low-density and high-density global areas, which is caused by the fogging effect. The developed simulator demonstrates that the simulator can be applied for all CD performance analyses and has the potential to be a mainstream device for EB lithography simulation.