Tadahiko Takikawa

EUVL practical mask structure with light shield area for 32nm half pitch and beyond

The effect of mask structure with light shield area on the printability in EUV lithography was studied. When very thin absorber on EUVL mask is used for ULSI application, it then becomes necessary to create EUV light shield area on the mask in order to suppress possible leakage of EUV light from neighboring exposure shots. We proposed and fabricated two types of masks with very thin absorber and light shield area structure. For both types of masks we demonstrated high shield performances at light shield areas by employing a Small Field Exposure Tool (SFET).

Primary evaluation of proximity and resist heating effects observed in high-acceleration voltage e-beam writing for 180-nm-and-beyond rule reticle fabrication

Higher resolution and accuracy are required in e-beam lithography for reticle fabrication for coping with further advances in optical lithography. The trend is to use high acceleration voltage (50 kV) e-beam to improve spatial resolution. However, in the case of high acceleration e-beam writing, a drastic critical dimension (CD) change is caused by a strong proximity effect and a large resist heating effect. The proximity effect is caused by the increase in the back- scattering radius. The back-scattering radius was estimated by two independent observations of the CD variation of a monitor and the thickness variation of a partially developed resist. It is found to be ca. 15 nm. Using the shot time modulation as a proximity correction reduced the proximity effect to a small level: CD error due to the pattern density change remained within 10 nm. On the other hand, the resist heating effect is caused by the change in resist dissolution speed by the temperature rise of the resist. In reducing this effect, multi-pass writing is found to be effective. The range of the CD error of 2 micrometer lines-and-spaces in the writing field has been reduced from 22 nm to 6 nm by changing the writing from one pass to four passes for a conventional resist. Moreover, when a chemically amplified resist (CAR) is exposed through one-pass writing, the range of the CD error is found to be 8 nm. Therefore, the use of the CAR is effective in reducing the resist heating effect. Simulation software ProBEAM/3D and TEMPTATION were used to obtain three- dimensional resist profile and the transient temperature rise of the resist, respectively. Both provided results that agreed well with those by experiment.

Particle-free mask handling techniques and a dual-pod carrier

In EUV lithography, particle-free handling is one of the critical issues because a pellicle is impractical due to its high absorption. To investigate this subject, we have developed a mask protection engineering tool that allows various types of tests to be carried out during the transfer of a mask or blank in air and in vacuum. We measured the number of particle adders during the transfer of a mask blank in a dual-pod carrier and in an RSP200 carrier. We found that the number of particle adders (>=46 nm PSL) to a mask blank in a dual pod is less than 0.01 over the whole process from taking the blank out of the load port in air to putting it in the electrostatic chuck chamber in vacuum. Through various experiments, the number of particle adders during any process using a dual pod was found to be very few and very stable. In contrast, for a naked mask, many particle adders were found in large variations. Below one particle were added in over 80% of experiments on a dual pod and in about 20% of experiments on a naked mask. Based on the test results, we can conclude that the use of dual pod is an excellent particle-free transfer technique.

Demonstration of defect free EUV mask for 22nm NAND flash contact layer using electron beam inspection system

Fabrication of defect free EUV masks including their inspection is the most critical challenge for implementing EUV lithography into semiconductor high volume manufacturing (HVM) beyond 22nm half-pitch (HP) node. The contact to bit-line (CB) layers of NAND flash devices are the most likely the first lithography layers that EUV will be employed for manufacturing due to the aggressive scaling and the difficulty for making the pattern with the current ArF lithography. To assure the defect free EUV mask, we have evaluated electron beam inspection (EBI) system eXplore™ 5200 developed by Hermes Microvision, Inc. (HMI) [1]. As one knows, the main issue of EBI system is the low throughput. To solve this challenge, a function called Lightning Scan™ mode has been recently developed and installed in the system, which allows the system to only inspect the pattern areas while ignoring blanket areas, thus dramatically reduced the overhead time and enable us to inspect CB layers of NAND Flash device with much higher throughput. In this present work, we compared the Lightning scan mode with Normal scan mode on sensitivity and throughput. We found out the Lightning scan mode can improve throughput by a factor of 10 without any sacrifices of sensitivity. Furthermore, using the Lightning scan mode, we demonstrated the possibility to fabricate the defect free EUV masks with moderate inspection time.

Electron beam inspection of 16nm HP node EUV masks

EUV lithography (EUVL) is the most promising solution for 16nm HP node semiconductor device manufacturing and beyond. The fabrication of defect free EUV mask is one of the most challenging roadblocks to insert EUVL into high volume manufacturing (HVM). To fabricate and assure the defect free EUV masks, electron beam inspection (EBI) tool will be likely the necessary tool since optical mask inspection systems using 193nm and 199nm light are reaching a practical resolution limit around 16nm HP node EUV mask. For production use of EBI, several challenges and potential issues are expected. Firstly, required defect detection sensitivity is quite high. According to ITRS roadmap updated in 2011, the smallest defect size needed to detect is about 18nm for 15nm NAND Flash HP node EUV mask. Secondly, small pixel size is likely required to obtain the high sensitivity. Thus, it might damage Ru capped Mo/Si multilayer due to accumulated high density electron beam bombardments. It also has potential of elevation of nuisance defects and reduction of throughput. These challenges must be solved before inserting EBI system into EUV mask HVM line. In this paper, we share our initial inspection results for 16nm HP node EUV mask (64nm HP absorber pattern on the EUV mask) using an EBI system eXplore® 5400 developed by Hermes Microvision, Inc. (HMI). In particularly, defect detection sensitivity, inspectability and damage to EUV mask were assessed. As conclusions, we found that the EBI system has capability to capture 16nm defects on 64nm absorber pattern EUV mask, satisfying the sensitivity requirement of 15nm NAND Flash HP node EUV mask. Furthermore, we confirmed there is no significant damage to susceptible Ru capped Mo/Si multilayer. We also identified that low throughput and high nuisance defect rate are critical challenges needed to address for the 16nm HP node EUV mask inspection. The high nuisance defect rate could be generated by poor LWR and stitching errors during EB writing of 64nm HP resist pattern. This result suggests we need further improvements not only in the EBI inspection system but also the patterning processes for 16nm HP node EUV masks.

Development of a novel EUV mask protection engineering tool and mask handling techniques

We have developed a mask protection engineering tool (MPE Tool) that simulates various types of tests during the transfer of a mask or blank in air and in vacuum. We performed mask transfer experiments to investigate particle-free mask handling techniques using the MPE and mask inspection tools. We measured the number of particles accumulated during the transfer of the mask blanks. Less than 0.3 particles were added over a path from a load port (in air) to an ESC chamber (in vacuum) and more than half the particles accumulated appeared during the pumping down and purging steps in the load-lock chamber. Consequently, we consider that pumping down and purging are the most important steps for particle-free mask handling.

A novel mask proximity correction software combining accuracy and reduced writing time for the manufacturing of advanced photomasks

The new generations of photomasks are seen to bring more and more challenges to the mask manufacturer. Maskshops face two conflicting requirements, namely improving pattern fidelity and reducing or at least maintaining acceptable writing time. These requirements are getting more and more challenging since pattern size continuously shrinks and data volumes continuously grows. Although the classical dose modulation Proximity Effect Correction is able to provide sufficient process control to the mainstream products, an increased number of published and wafer data show that the mask process is becoming a nonnegligible contributor to the 28nm technology yield. We will show in this paper that a novel approach of mask proximity effect correction is able to meet the dual challenge of the new generation of masks. Unlike the classical approach, the technique presented in this paper is based on a concurrent optimization of the dose and geometry of the fractured shots. Adding one more parameter allows providing the best possible compromise between accuracy and writing time since energy latitude can be taken into account as well. This solution is implemented in the Inscale software package from Aselta Nanographics. We have assessed the capability of this technology on several levels of a 28nm technology. On this set, the writing time has been reduced up to 25% without sacrificing the accuracy which at the same time has been improved significantly compared to the existing process. The experiments presented in the paper confirm that a versatile proximity effect correction strategy, combining dose and geometry modulation helps the users to tradeoff between resolution/accuracy and e-beam write time.

Native pattern defect inspection of EUV mask using advanced electron beam inspection system

Fabrication of defect free EUV mask is one of the most critical roadblocks for implementing EUV lithography into semiconductor high volume manufacturing for 22nm half-pitch (HP) node and beyond. At the same time, development of quality assurance process for the defect free EUV mask is also another critical challenge we need to address before the mass production. Inspection tools act important role in quality assurance process to ensure the defect free EUV mask. We are currently evaluating two types of inspection system: optical inspection (OPI) system and electron beam inspection (EBI) system [1, 2]. While OPI system is sophisticated technology and has an advantage in throughput, EBI system is superior in sensitivity and extendability to even small pattern. We evaluated sensitivity of EBI system and found it could detect 25 nm defects on 88nm L/S pattern which is as small as target defect size for 23 nm Flash HP pattern in 2013 in 2009 ITRS lithography roadmap [2, 3]. EBI system is effective inspection tool even at this moment to detect such small defects on 88nm HP pattern, though there are still some challenges such as the slow throughput and the reliability. Therefore, EBI system can be used as bridge tool to compensate insufficient sensitivity of current inspection tools and improve EUV mask fabrication process to achieve the defect free EUV mask. In this paper, we will present the results of native pattern defects founded on large field 88nm HP pattern using advance EBI system. We will also classify those defects and propose some ideas to mitigate them and realize the defect free EUV mask, demonstrating the capability of EBI as bridge tool.

Thin-absorber extreme-ultraviolet lithography mask with light-shield border for full-field scanner: flatness and image placement change through mask process

When a thinner absorber mask is practically applied to the extreme ultraviolet lithography for ultra large scale integration chip production, it is inevitable to introduce an extreme ultraviolet (EUV) light shield area to suppress leakage of the EUV light from adjacent exposure shots. We believe that a light-shield border of the multilayer etching type is a promising structure in terms of mask process flexibility for higher mask critical dimension accuracy. We evaluate the etching impact of the absorber and multilayer on the mask flatness and image placement change through the mask process of a thin absorber mask with a light-shield border of the multilayer etching type structure. We clarify the relation between mask flatness and mask image placement shift.

NGL masks: development status and issue

Semiconductor lithography candidates toward 2xnm node and beyond include wide variety of options, such as extension of 193i, EUVL, NIL, and ML2. Most of those candidates, except ML2, need critical mask feature to realize effective high volume manufacturing. In this presentation, EUVL mask technology update and future issues will be presented.