Naomu Kitano

Excellent electrical properties of TiO2∕HfSiO∕SiO2 layered higher-k gate dielectrics with sub-1nm equivalent oxide thickness

Equivalent oxide thickness (EOT) scaling, as well as improved interface properties, of metal/higher-k gate stacks for the sub-1nm region was achieved using a TiO2∕HfSiO∕SiO2 layered dielectric structure. Ti diffusion into the bottom oxides was found to form electrical defects, which lead to an increase of leakage current, fixed charge, interface trap density (Dit), and reliability degradation of the gate stacks. By controlling Ti diffusion and terminating Ti-induced defects using forming gas annealing, we successfully obtained a superior interface property (Dit=9.9×1010eV−1cm−2) and reduced gate leakage (Jg=7.2×10−2A∕cm2) at the 0.71-nm-EOT region.

Charge trapping properties in TiO2∕HfSiO∕SiO2 gate stacks probed by scanning capacitance microscopy

The charge-trapping properties of the high-permittivity titanium oxide–hafnium silicate–silicon dioxide (TiO2∕HfSiO∕SiO2) gate stacks have been studied using scanning capacitance microscopy. From the bias stress examination of the gate stacks, we concluded that there were electron traps within the films, and these trap densities increased with an increase in the oxidation temperature used for the fabrication of TiO2 top dielectrics. Furthermore, we found that the distribution of these charged defects was inhomogeneous within the gate stacks. These results are attributed to Ti diffusion through the dielectric layers, which caused electrical defects within the gate stacks.

Impact of Physical Vapor Deposition-Based In situ Fabrication Method on Metal/High-k Gate Stacks

We proposed an in situ method for fabricating metal/high-k gate stacks. High-quality Hf silicate gate dielectrics were formed by utilizing a solid phase interface reaction (SPIR) between a metal Hf layer and an SiO2 underlayer, and TiN electrodes were continuously grown on the gate dielectrics using a low-damage sputtering system without exposure to air. We investigated the optimum SPIR conditions for TiN/HfSiO gate stacks, such as the thicknesses of the metal Hf and oxide underlayers, in situ annealing temperature, and oxygen pressure. The results indicate that the in situ method can be used to precisely control the SPIR to form silicate films and improve the electrical properties at metal/high-k interfaces. We demonstrated that the scaling of equivalent oxide thickness (EOT) was achieved and that the carbon impurity content at the gate stacks was successfully reduced by in situ silicate formation and continuous electrode deposition. As a consequence, we obtained excellent EOT versus gate leakage characteristics and succeeded in improving the hysteresis of capacitance–voltage curves for the TiN/HfSiO gate stacks.

Fabrication of advanced La-incorporated Hf-silicate gate dielectrics using physical-vapor-deposition-based in situ method and its effective work function modulation of metal/high-k stacks

Lanthanum (La) incorporation into Hf-silicate high-permittivity (high-k) gate dielectrics was conducted using a physical-vapor-deposition (PVD)-based in situ method. PVD-grown metal Hf, La, and Hf–La alloys on base SiO2 oxides received in situ annealing to form high-quality HfLaSiO dielectrics, and subsequent deposition of metal gate electrodes was carried out to fabricate advanced metal/high-k gate stacks without breaking vacuum. The in situ method was found to precisely control La content and its depth profile and to tune the effective work function of metal/high-k stacks. Remarkable leakage current reduction of almost seven orders of magnitude compared with conventional poly-Si/SiO2 stacks and excellent interface properties comparable to an ideal SiO2/Si interface were also achieved at an equivalent oxide thickness of around 1.0 nm. Our x-ray photoelectron spectroscopy analysis revealed that, as previously suggested, effective work function modulation due to La incorporation is attributed to the interf...

Detrimental Hf penetration into TiN gate electrode and subsequent degradation in dielectric properties of HfSiO high-k film

Hafnium penetration through the TiN gate electrode as thick as 10 nm is detected in the TiN/HfSiO/SiO2 gate stacks after high-temperature annealing by using x-ray photoelectron spectroscopy. The Hf outdiffusion, showing TiN thickness dependence, is revealed to cause permittivity lowering of the pristine HfSiO high-k layer, which accelerates the equivalent oxide thickness increase and degrades the dielectric properties. In contrast, such diffusion is suppressed by adopting metal inserted polycrystalline silicon stack (MIPS) structure. Our further experiments indicate that the SiO2 regrowth during high-temperature annealing, which is hampered in MIPS structure, triggers the adverse Hf diffusion.

Enhanced Performance of Gate-First p-Channel Metal-Insulator-Semiconductor Field-Effect Transistors with Polycrystalline Silicon/TiN/HfSiON Stacks Fabricated by Physical Vapor Deposition Based In situ Method

We demonstrated the use of an in situ metal/high-k fabrication method for improving the performance of metal–insulator–semiconductor field-effect transistors (MISFETs). Gate-first pMISFETs with polycrystalline silicon (poly-Si)/TiN/HfSiON stacks were fabricated by techniques based on low-damage physical vapor deposition, in which high-quality HfSiON dielectrics were formed by the interface reaction between an ultrathin metal-Hf layer (0.5 nm thick) and a SiO2 underlayer, and TiN electrodes were continuously deposited on the gate dielectrics without exposure to air. Gate-first pMISFETs with high carrier mobility and a low threshold voltage (Vth) were realized by reducing the carbon impurity in the gate stacks and improving the Vth stability against thermal treatment. As a result, we obtained superior current drivability (Ion = 350 µA/µm at Ioff = 200 pA/µm), which corresponds to a 13% improvement over that of conventional chemical vapor deposition-based metal/high-k devices.

Oxygen-induced high-k degradation in TiN/HfSiO gate stacks

We have investigated the diffusion kinetics of Hf in TiN/HfSiO gate stacks. The Hf upward diffusion is found to be independent of interfacial SiO2 growth, but depends on the amount of oxygen in the gate stacks. It is also revealed that Hf diffusion into TiN electrode occurs at above 650°C and leads to high-k degradation.

High Performance Gate-First pMISFET with TiN/HfSiON Gate Stacks Fabricated with PVD-Based In-Situ Method

Fermi-level pinning on Hf-based high-k with poly-Si, resulting in high and uncontrollable threshold voltage (Vth) especially in pMIS, has been a serious concern. Therefore, cost-worthy and high-performance LSTP cMISFETs with poly-Si/HfSiON nMIS and polySi/TiN/HfSiON pMIS have been studied [1,2]. In these references, HfSiON and TiN films were formed by CVD methods, respectively [3,4], and these films include some impurities such as Cl and C from CVD sources and air. It has already been reported that the residual impurities in the high-k gate stack degraded the device performance [5]. Then, PVD-based in-situ method for TiN/HfSiON stack is much attractive because it can minimize the impurities both within HfSiON layer and metal/high-k interface. This method is as follows; PVD-grown metalHf layer on SiO2 underlayer was fully consumed by annealing of solid phase interface reaction (SPIR) to form Hf-silicate [6], and TiN film was continuously grown on the Hf-silicate with low-damage PVD without exposure to air [7]. In this work, we investigated the effects of this PVD-based in-situ method on the pMISFET properties, comparing with the usual ex-situ CVD methods. P-doped poly-Si films were grown on these TiN /HfSiON stacks by an ex-situ CVD. MISFETs were fabricated by a conventional gate-first process that includes gate dry etching and spike-RTA up to 1050oC. Vg-Id&Ig curves and Vth roll-off characteristics of polySi/TiN/HfSiON stacks fabricated by different 3 processes, 1) ex-situ CVD-TiN on CVD-HfSiON, 2) ex-situ PVDTiN on CVD-HfSiON, and 3) in-situ PVD-TiN on SPIRHfSiON, were shown in Figs. 1 and 2. These indicate that the suitable subthreshold swing (S) of 1) 65.0, 2) 66.4, and 3) 65.5 mV/dec could be obtained, and that the Vthvalues were 1) -0.64, 2) -0.46, and 3) -0.44V at Lg=10μm, respectively. PVD-TiN could provide relatively low Vth, probably because PVD-TiN had less impurity and better film quality than CVD-TiN, and it could restrain the diffusion of Si from poly-Si to high-k [4]. SPIR-HfSiON and in-situ process could reduce Vth more, probably due to the reduction of C impurity both within HfSiON layer and metal/high-k interface. On the other hand, fluorine ion implantation into the substrate has been reported that it was an attractive method for controlling Vth in pMIS [3]. Figure 3 shows the comparison of Ion-Ioff characteristics between different 3 processes, a) ex-situ CVD-TiN on CVD-HfSiON, b) exsitu CVD-TiN on CVD-HfSiON with substrate fluorine ion implantation, and c) in-situ PVD-TiN on SPIRHfSiON. As the amount of F implantation increases, Vth is reduced, however, when too much F was implanted, IonIoff characteristics deteriorated as shown in Fig. 3. This is probably due to the deterioration of S-value [8]. The PVD-based in-situ method could provide Ion=350μA/μm at Ioff=200pA/μm, which was a 15% improvement over ex-situ CVD-TiN on CVD-HfSiON. Other superior pMISFET properties, such as Vth, S-value, hole mobility, and gate leakage current, could also be obtained, because this in-situ method could minimize the impurities. Moreover, this PVD-based in-situ method with moderate F implantation would reduce Vth even more without deterioration of Ion.

Impact of Thermally Induced Structural Changes on the Electrical Properties of TiN/HfLaSiO Gate Stacks

Thermally induced structural changes in TiN/Hf(La)SiO gate stacks were investigated by back-side X-ray photoelectron spectroscopy (XPS) and near edge X-ray absorption fine structure (NEXAFS). A distinct correlation between bottom oxide growth and an increase in equivalent oxide thickness (EOT) was confirmed under high-temperature annealing at over 850 °C regardless of La content. Back-side XPS also revealed that oxygen and nitrogen diffusion occurs, forming partially oxidized TiON layers at a metal/high-k interface under moderate annealing temperatures of approximately 600 °C, and that annealing at over 750 °C leads to the reduction of the oxide phase and produces a thinner inter-layer with a clear Ti–N bond feature. Moreover, with an increase in annealing temperature, a change in the local atomic configuration in the HfLaSiO dielectric layer was identified from oxygen K-edge spectra. This structural change induced by thermal reaction can be considered as a possible cause of the Vth instability of La-incorporated high-k gate stacks. On the basis of these findings on structural changes, the physical origins of the effective work function modulation of the gate stacks are discussed in detail.

La Induced Passivation of High-k Bulk and Interface Defects in Polycrystalline Silicon/TiN/HfLaSiO/SiO2 Stacks

La incorporation into Hf-based gate dielectrics is a promising methodology for achieving low threshold voltage (Vth) metal/high-k n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) with the gate-first process. To clarify the impact of the Hf/La ratio in high-k dielectrics on device performance, we investigated high-k bulk and interface traps of polycrystalline silicon (poly-Si)/TiN/HfLaSiO/SiO2 stacks with various Hf/La ratios. We found that La incorporation is effective for improving electron mobility; however, in a pure LaSiO device, the mobility is degraded. Our charge-pumping (CP) measurements revealed that both high-k bulk traps and near-interface traps (Nit) near the conduction band, which cause mobility degradation, can be effectively passivated by La incorporation. These results imply that an optimized La ratio will lead to superior nMOSFET performance, while an appropriate Vth can be tuned.