Shinya Horie

Hydrogen termination of Si(110) surfaces upon wet cleaning revealed by highly resolved scanning tunneling microscopy

The surface structure of the hydrogen-saturated Si(110) surfaces after wet cleaning is studied on an atomic scale by means of scanning tunneling microscopy. When a surface oxide layer is stripped using a HF-containing solution, the surface consists of nanometer-scaled terraces and atomic steps along various directions. Coupled monohydride lines are formed inside a small terrace, as predicted by infrared spectra. The Si(110) surface after subsequent rinsing for a short period is occupied by a long terrace along the [1¯10] direction in which the ideal 1×1 structure is formed. Atomic arrangements around step edges are determined in detail based on atomic images and first-principles calculations. A ridge-shaped structure is observed after excess rinsing with water, and infrared spectra indicate that the slope is composed of (111) microfacets. From these results, we present the mechanism underlying the formation of the hydrogen-terminated Si(110) surfaces during wet cleaning processes.

Charge trapping properties in TiO2∕HfSiO∕SiO2 gate stacks probed by scanning capacitance microscopy

The charge-trapping properties of the high-permittivity titanium oxide–hafnium silicate–silicon dioxide (TiO2∕HfSiO∕SiO2) gate stacks have been studied using scanning capacitance microscopy. From the bias stress examination of the gate stacks, we concluded that there were electron traps within the films, and these trap densities increased with an increase in the oxidation temperature used for the fabrication of TiO2 top dielectrics. Furthermore, we found that the distribution of these charged defects was inhomogeneous within the gate stacks. These results are attributed to Ti diffusion through the dielectric layers, which caused electrical defects within the gate stacks.

Impact of Physical Vapor Deposition-Based In situ Fabrication Method on Metal/High-k Gate Stacks

We proposed an in situ method for fabricating metal/high-k gate stacks. High-quality Hf silicate gate dielectrics were formed by utilizing a solid phase interface reaction (SPIR) between a metal Hf layer and an SiO2 underlayer, and TiN electrodes were continuously grown on the gate dielectrics using a low-damage sputtering system without exposure to air. We investigated the optimum SPIR conditions for TiN/HfSiO gate stacks, such as the thicknesses of the metal Hf and oxide underlayers, in situ annealing temperature, and oxygen pressure. The results indicate that the in situ method can be used to precisely control the SPIR to form silicate films and improve the electrical properties at metal/high-k interfaces. We demonstrated that the scaling of equivalent oxide thickness (EOT) was achieved and that the carbon impurity content at the gate stacks was successfully reduced by in situ silicate formation and continuous electrode deposition. As a consequence, we obtained excellent EOT versus gate leakage characteristics and succeeded in improving the hysteresis of capacitance–voltage curves for the TiN/HfSiO gate stacks.

First-principles study on scanning tunneling microscopy images of different hydrogen-terminated Si(110) surfaces

Scanning tunneling microscopy images of various hydrogen-terminated Si(110) flat surfaces and surfaces with steps, isolated monohydride row, and missing monohydride row are studied using first-principles calculations. Our results show that the calculated filled-state images and local density of states are consistent with recent experimental results, and the empty-state images appear significantly different from the filled-state ones in every model. To elucidate the origin of this difference, we examined in detail the local density of states, which affects the images, and found that the difference is largely attributed to the characteristics of the bonding and antibonding states of surface silicon atoms.

High Performance Gate-First pMISFET with TiN/HfSiON Gate Stacks Fabricated with PVD-Based In-Situ Method

Fermi-level pinning on Hf-based high-k with poly-Si, resulting in high and uncontrollable threshold voltage (Vth) especially in pMIS, has been a serious concern. Therefore, cost-worthy and high-performance LSTP cMISFETs with poly-Si/HfSiON nMIS and polySi/TiN/HfSiON pMIS have been studied [1,2]. In these references, HfSiON and TiN films were formed by CVD methods, respectively [3,4], and these films include some impurities such as Cl and C from CVD sources and air. It has already been reported that the residual impurities in the high-k gate stack degraded the device performance [5]. Then, PVD-based in-situ method for TiN/HfSiON stack is much attractive because it can minimize the impurities both within HfSiON layer and metal/high-k interface. This method is as follows; PVD-grown metalHf layer on SiO2 underlayer was fully consumed by annealing of solid phase interface reaction (SPIR) to form Hf-silicate [6], and TiN film was continuously grown on the Hf-silicate with low-damage PVD without exposure to air [7]. In this work, we investigated the effects of this PVD-based in-situ method on the pMISFET properties, comparing with the usual ex-situ CVD methods. P-doped poly-Si films were grown on these TiN /HfSiON stacks by an ex-situ CVD. MISFETs were fabricated by a conventional gate-first process that includes gate dry etching and spike-RTA up to 1050oC. Vg-Id&Ig curves and Vth roll-off characteristics of polySi/TiN/HfSiON stacks fabricated by different 3 processes, 1) ex-situ CVD-TiN on CVD-HfSiON, 2) ex-situ PVDTiN on CVD-HfSiON, and 3) in-situ PVD-TiN on SPIRHfSiON, were shown in Figs. 1 and 2. These indicate that the suitable subthreshold swing (S) of 1) 65.0, 2) 66.4, and 3) 65.5 mV/dec could be obtained, and that the Vthvalues were 1) -0.64, 2) -0.46, and 3) -0.44V at Lg=10μm, respectively. PVD-TiN could provide relatively low Vth, probably because PVD-TiN had less impurity and better film quality than CVD-TiN, and it could restrain the diffusion of Si from poly-Si to high-k [4]. SPIR-HfSiON and in-situ process could reduce Vth more, probably due to the reduction of C impurity both within HfSiON layer and metal/high-k interface. On the other hand, fluorine ion implantation into the substrate has been reported that it was an attractive method for controlling Vth in pMIS [3]. Figure 3 shows the comparison of Ion-Ioff characteristics between different 3 processes, a) ex-situ CVD-TiN on CVD-HfSiON, b) exsitu CVD-TiN on CVD-HfSiON with substrate fluorine ion implantation, and c) in-situ PVD-TiN on SPIRHfSiON. As the amount of F implantation increases, Vth is reduced, however, when too much F was implanted, IonIoff characteristics deteriorated as shown in Fig. 3. This is probably due to the deterioration of S-value [8]. The PVD-based in-situ method could provide Ion=350μA/μm at Ioff=200pA/μm, which was a 15% improvement over ex-situ CVD-TiN on CVD-HfSiON. Other superior pMISFET properties, such as Vth, S-value, hole mobility, and gate leakage current, could also be obtained, because this in-situ method could minimize the impurities. Moreover, this PVD-based in-situ method with moderate F implantation would reduce Vth even more without deterioration of Ion.

First-principles study of the tunnel current between a scanning tunneling microscopy tip and a hydrogen-adsorbed Si(001) surface

A scanning tunneling microscopy (STM) image of a hydrogen-adsorbed

Low Threshold Voltage Gate-First pMISFETs with Poly-Si/TiN/HfSiON Stacks Fabricated with PVD-based In-situ Solid Phase Interface Reaction (SPIR) Method

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First-principles calculation of tunneling current of H2- or NH3-adsorbed Si(001) surface in scanning tunneling microscopy

surface is studied using first-principles electron-conduction calculation. The resultant STM image and scanning tunneling spectroscopy spectra are in agreement with experimental results. The contributions of the

Structural optimization of HfTiSiO high-k gate dielectrics by utilizing in-situ PVD-based fabrication method

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Interface Engineering by PVD-Based In-Situ Fabrication Method for Advanced Metal/High-k Gate Stacks

states of bare dimers to the tunnel current are markedly large, and the