Hiroaki Arimura

Reliability in gate first and gate last ultra-thin-EOT gate stacks assessed with CV-eMSM BTI characterization

CMOS device improvements have recently been achieved by aggressive scaling of effective oxide thickness (EOT) in Gate First (GF) integration schemes using interfacial layer scavenging. Along with this scaling comes, however, a challenging reliability penalty. Therefore, to decrease the turnaround time of experimental gate stacks, we demonstrate a technique to quantitatively evaluate the long-term bias temperature instability (BTI) behavior of gate stacks on capacitors instead of transistors. We prove that this technique yields comparable results as standard extended measure-stress-measure (eMSM) IV-BTI measurements. Subsequently, we demonstrate in such a short turnaround time experiment that we can achieve scavenging in a Gate Last (GL) processing scheme. Finally, by benefitting from our proposed technique, we conclude that our Gate Last stacks are still more susceptible to BTI than our Gate First stacks with similar EOT.

Beyond-Si materials and devices for more Moore and more than Moore applications

In this work, we will review the current progress in high mobility devices and new device architectures. With main focus on (Si)Ge for pMOS and In(Ga)As for nMOS, the benefits and challenges of integrating these materials on a Si platform will be discussed. Next to that, the advantages of tunnel FETs, vertical logic and in general heterogeneous integration will be highlighted.

Advanced channel materials for the semiconductor industry

In this work, we will review the current progress in integration and device design of high mobility devices. With main focus on (Si)Ge for pMOS and In(Ga)As for nMOS, the benefits and challenges of integrating these materials on a Si platform will be discussed.