Naonobu Sukegawa

A powerful yet ecological parallel processing system using execution-based adaptive power-down control and compact quadruple-precision assist FPUs

This paper reports the first trial in which spatially and temporally fine-grained power-down control has been implemented in a high-performance processor in the sense that the FPUs are controlled spatially and dynamically based on the execution sequence.

Design and Power Performance Evaluation of On-Chip Memory Processor with Arithmetic Accelerators

In this paper, we design an on-chip memory processor with arithmetic accelerators, which are expected to improve power consumption. In addition, we evaluate the power performance of the processor. We propose implementing vector-type arithmetic accelerators and SIMD-type arithmetic accelerators in the on-chip memory processor. The evaluation results obtained using our simulator indicate that the performance of the 4FMAs SIMD-type accelerators is similar to that of the 4FMAs vector-type accelerators on DAXPY, Livermore kernel 1 and 3. However, the performance of the 4FMAs vector-type accelerator exceeds that of the 4FMAs SIMD-type accelerator with respect to matrix multiplication and QCD because of difference in element size of the registers. On Livermore kernel 7, the power performance of the 4FMAs SIMD-type accelerators exceeds that of the 4FMAs vector-type because of register reuse. However, the 16FMAs vector-type accelerators have an advantage in almost all simulations, excluding main memory bandwidth intensive benchmarks.