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Dive into the research topics where Naotaka Uchitomi is active.

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Featured researches published by Naotaka Uchitomi.


Japanese Journal of Applied Physics | 1994

Refractory WNx/W Self-Aligned Gate GaAs Power Metal-Semiconductor Field-Effect Transistor for 1.9-GHz Digital Mobile Communication System Operating with a Single Low-Voltage Supply

Masami Nagaoka; Kenji Ishida; Tokuhiko Matsunaga; Kazuya Nishihori; Takashi Hashimoto; Misao Yoshimura; Yoshikazu Tanabe; Masakatsu Mihara; Yoshiaki Kitaura; Naotaka Uchitomi

We have developed a refractory WNx /W self-aligned gate GaAs power metal-semiconductor field-effect transistor (MESFET) for use in L-band digital mobile communication systems. This power MESFET operates with high efficiency and low distortion at a gate bias of 0 V and a low drain bias of 2.7 V, because of its small drain knee voltage, high transconductance and sufficient breakdown voltage. This power MESFET is quite promising for a highly efficient linear power amplifier IC operating with a single low-voltage supply. Good output characteristics of the power MESFET with 1 mm gate width were attained for π/4-shifted quadrature phase shift keying (QPSK) modulated input signals in the 1.9-GHz band, such as an output power of 18.4 dBm, a power gain of 19.0 dB and a high power-added efficiency of 26.4% when a sufficiently low adjacent channel leakage power of -58 dBc was obtained.


IEEE Transactions on Electron Devices | 1998

A self-aligned gate GaAs MESFET with p-pocket layers for high-efficiency linear power amplifiers

Kazuya Nishihori; Yoshiaki Kitaura; Mayumi Hirose; Masakatsu Mihara; Masami Nagaoka; Naotaka Uchitomi

This paper describes a newly developed GaAs metal semiconductor field-effect transistor (MESFET)-termed p-pocket MESFET-for use as a linear power amplifier in personal handy-phone systems. Conventional buried p-layer technology, the primary technology for microwave GaAs power MESFETs, has a drawback of low power efficiency for linear power applications. The low power efficiency of the buried p-layer MESFET is ascribed to the I-V kink which is caused by holes collected in the buried p-layer under the channel. In order to overcome this problem, we have developed the self-aligned gate p-pocket MESFET which incorporates p-layers not under the channel but under the source and drain regions. This new MESFET exhibited high transconductance and uniform threshold voltage. The problematic I-V kink was successfully removed and an improved power efficiency of 48% was achieved under bias conditions, which resulted in adjacent channel leakage power at 600-kHz offset as low as -59 dBc for 1.9-GHz /spl pi//4-shift QPSK modulated input.


Journal of Applied Physics | 2016

Large As sublattice distortion in sphalerite ZnSnAs2 thin films revealed by x-ray fluorescence holography

Kouichi Hayashi; Naotaka Uchitomi; Keitaro Yamagami; Akiko Suzuki; Hayato Yoshizawa; Joel T. Asubar; Naohisa Happo; Shinya Hosokawa

The structure of a ZnSnAs2 thin film epitaxially grown on an InP substrate was evaluated using x-ray fluorescence holography. The reconstructed three-dimensional atomic images clearly show that the crystal structure of the ZnSnAs2 thin film is mainly of the sphalerite type, in contrast to the bulk form. A large disordering of the As layers is observed, whereas the positions of the Zn/Sn atoms are relatively stable. The analysis of the data indicates that the As layers serve as a buffer and relax the strain caused by the random occupation of Zn and Sn atoms. These results provide further understanding and a means of controlling the growth of Mn-doped ZnSnAs2, a high- Tc diluted magnetic semiconductor.


Japanese Journal of Applied Physics | 2008

Electrotransport Properties of p-ZnSnAs2 Thin Films Grown by Molecular Beam Epitaxy on Semi-insulating (001) InP Substrates

Joel T. Asubar; Ariyuki Kato; Yoshio Jinbo; Naotaka Uchitomi

ZnSnAs2 thin films were prepared by molecular beam epitaxy (MBE) on semi-insulating (001) InP substrates using the same growth conditions as previously reported. High-resolution X-ray diffractometry (HRXRD) and Raman spectroscopy studies suggest the presence of both the chalcopyrite and sphalerite phases. The transport properties were measured from 5 K up to room temperature. We observed a pronounced peak in the Hall coefficient temperature dependence curve at ~130 K, similar to those observed only from chalcopyrite-phase bulk ZnSnAs2 in earlier studies. A hole concentration of p = 5.98 ×1018 cm-3, hole mobility of µ= 23.61 cm2/(Vs) and resistivity of ρ= 4.43 ×10-2 Ωcm were obtained at room temperature.


Japanese Journal of Applied Physics | 1990

Mobility Profiles in Submicron WNx-BPLDD-GaAs MESFETs

Klaus Steiner; Naotaka Uchitomi; Nobuyuki Toyoda

The drift mobility profile in a submicron WNx-BPLDD (buried ptype buffer lightly doped drain region) GaAs MESFET with a highly doped buffer layer is evaluated using frequency-dependent admittance studies. A drift mobility maximum of 2300 cm2/Vs at a background carrier concentration level of 8×1017 cm-3 was determined. The investigations provide a convenient method for controlling transport properties in GaAs LSIs.


Japanese Journal of Applied Physics | 2010

Contribution of Carbon to Activation and Diffusion of Boron in Silicon

Hiroshi Itokawa; Yuji Agatsuma; Nobutoshi Aoki; Naotaka Uchitomi; Ichiro Mizushima

It is well-known that the coimplantation of carbon (C) in a concentration range comparable to the range of boron (B) concentrations could suppress B diffusion, resulting in a boxlike B profile. Substitutional C atoms can capture excess self-interstitial Si atoms and suppress the diffusion of ion-implanted intersitial-type dopants such as B in silicon (Si). However, the effect of C on activation properties in wide C and B concentration ranges has not been sufficiently investigated. In this work, in the experiment in wide C and B concentration ranges, it was clarified for the first time that the B activation ratio of Si increases or decreases varies depending on the concentration of C incorporated. The activation ratio of the B activation layer was increased markedly by C incorporation in the case of light B implantation such as in the concentration range of 8×1019 to 3×1020 cm-3. This might be attributed to the interaction of C with Si interstitials and the suppression of the boron Si-interstitial clustering induced by C incorporation. In contrast, in the case of heavy B implantation such as at a 1×1021 cm-3 concentration, the activation ratio was decreased slightly by C incorporation. When stable B-containing clusters and precipitates were formed at high B concentrations, the effect of C incorporation on activation ratio was considered to be small.


Japanese Journal of Applied Physics | 2005

Optical Characterization of Heavily Sn-Doped GaAs1-xSbx Epilayers Grown by Molecular Beam Epitaxy on (001) GaAs Substrates

Fumio Nishino; Tatsuya Takei; Ariyuki Kato; Yoshio Jinbo; Naotaka Uchitomi

We have optically investigated ternary GaAs1-xSbx (x<0.58) epilayers and Sn-doped GaAs1-xSbx (x=0.10–0.14) epilayers grown by molecular beam epitaxy on GaAs (001) substrates. Sn-doped GaAsSb layers were grown as a function of Sn Knudsen-cell temperature, and then characterized by low-temperature photoluminescence (PL) measurements and Hall effect measurements. The Sn-doped GaAsSb films grown at a K-cell temperature of 670°C changed from exhibiting p-type conduction to exhibiting n-type conduction, and showed a maximum PL intensity and a maximum electron mobility of 1900 cm2/V s. The PL intensities obtained for Sn-doped GaAsSb films showed a relatively good correlation with the variations in Hall mobility.


IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A | 1997

Thermal analysis of GaAs power monolithic microwave IC's mounted with epoxy attachment

Kazuya Nishihori; Kenji Ishida; Yoshiaki Kitaura; Naotaka Uchitomi

The effect of chip-mounting attachment on the thermal resistance of GaAs power field effect transistor (FET) modules has been experimentally investigated. The thermal resistance was evaluated for different GaAs chip thickness of 150 and 250 /spl mu/m through an electrical method utilizing temperature dependence of Schottky-barrier in the GaAs metal semiconductor FETs (MESFETs). The thermal resistance of low-cost epoxy-mounted GaAs chips, suitable for uniplanar monolithic microwave ICs (MMICs), was found not to increase even up to a chip thickness of 250 /spl mu/m, while that of AuSn-mounted GaAs chips increased as was conventionally expected. Numerical simulation has also been presented for the similar case of GaAs power MMICs. The result of simulation suggests that lower thermal conductivity of attachment material, such as epoxy attachment, leads to larger optimum chip thickness that minimizes the total thermal resistance.


Journal of Vacuum Science & Technology B | 1990

Inductive reactances and excess capacitances at WNx/n‐GaAs Schottky gate contacts

Klaus Steiner; Naotaka Uchitomi; Nobuyuki Toyoda

Minority carrier injection at forward‐biased WNx/n‐GaAs Schottky gates lead to diffusion capacitances in excess to the space charge capacitance and inductive reactances in certain frequency ranges. p‐buffer layers act as a minority carrier sink which enhances the minority carrier injection. This finally gives stronger excess capacitances and inductive reactances. Furthermore, excess diffusion capacitances can be observed at higher frequencies. The frequency dependent admittance behavior of forward biased WNx/n‐GaAs gates is studied in the temperature range between 77 K and room temperature.


Japanese Journal of Applied Physics | 2005

Defects Induced by Carbon Contamination in Low-Temperature Epitaxial Silicon Films Grown with Monosilane

Shinya Sato; Ichiro Mizushima; Kiyotaka Miyano; Tsutomu Sato; Shin-ichi Nakamura; Yoshitaka Tsunashima; Tsunetoshi Arikado; Naotaka Uchitomi

The structures of the defects induced by carbon contamination in epitaxial silicon films grown with monosilane (SiH4) on silicon substrates were investigated. A new formation mechanism of defects associated with carbon in silicon epitaxial growth processes is proposed. The carbon contaminants were introduced prior to the growth by chemical vapor deposition (CVD), where the growth chamber was intentionally contaminated with organic materials. The carbon contaminant concentration was changed by adjusting the annealing conditions at temperatures ranging from 900°C to 1100°C. Silicon epitaxial films were grown by CVD at a temperature of 700°C. In this experiment, we found that pits were formed as dominant surface defects under the condition of a relatively low carbon concentration of less than 4.5×1013 cm-2, while mound defects were formed at a carbon concentration of more than 4.5×1013 cm-2. These defects can be explained by the formation of silicon carbide (SiC) islands resulting from the carbon contamination.

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Yoshio Jinbo

Nagaoka University of Technology

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Hideyuki Toyota

Nagaoka University of Technology

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Joel T. Asubar

Nagaoka University of Technology

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Hiroto Oomae

Nagaoka University of Technology

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Shiro Hidaka

Nagaoka University of Technology

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