Yoshiaki Kitaura

A 10ghz Gaas 8b Multiplexer/demultiplexer Chip Set For The Sonet Sts-192 System

An ultrahigh-speed 8-b multiplexer (MUX) and demultiplexer (DMUX) chip set has been developed for the synchronous optical network (SONET) next-generation optical-fiber communication systems, which will require data bit rates of about 10 Gb/s. These ICs were designed using three novel concepts: a tree-type architecture giving reliable operation, a dynamic divider with a wide operating range, and a 50- Omega on-chip transmission line with high-speed pulse propagation. They were fabricated using a 0.5- mu m WN/sub x/-gate GaAs MESFET process. The DMUX and MUX operated at up to 10.4 and 11.4 GHz, respectively, both with an adequate phase margin of more than 230 degrees . >

A novel resonant-type GaAs SPDT switch IC with low distortion characteristics for 1.9 GHz personal handy-phone system

A GaAs SPDT switch IC operating at a low power supply voltage of 2.7 V has been developed for use in Personal Handy-Phone System in the 1.9 GHz band. In combination with MESFETs with low on-resistance and high breakdown voltage, the resonant-type switch IC utilizes stacked FETs and an additional shunt capacitor at the receiver side in order to realize low insertion loss, high isolation and low distortion characteristics. An insertion loss of 0.55 dB and an isolation of 35.8 dB were obtained at 1.9 GHz. The IC also achieved a second order distortion of -54.3 dBc and an adjacent channel leakage power of -66 dBc at 600 kHz apart from 1.9 GHz at 19 dBm output power.

Refractory WNx/W Self-Aligned Gate GaAs Power Metal-Semiconductor Field-Effect Transistor for 1.9-GHz Digital Mobile Communication System Operating with a Single Low-Voltage Supply

We have developed a refractory WNx /W self-aligned gate GaAs power metal-semiconductor field-effect transistor (MESFET) for use in L-band digital mobile communication systems. This power MESFET operates with high efficiency and low distortion at a gate bias of 0 V and a low drain bias of 2.7 V, because of its small drain knee voltage, high transconductance and sufficient breakdown voltage. This power MESFET is quite promising for a highly efficient linear power amplifier IC operating with a single low-voltage supply. Good output characteristics of the power MESFET with 1 mm gate width were attained for π/4-shifted quadrature phase shift keying (QPSK) modulated input signals in the 1.9-GHz band, such as an output power of 18.4 dBm, a power gain of 19.0 dB and a high power-added efficiency of 26.4% when a sufficiently low adjacent channel leakage power of -58 dBc was obtained.

A self-aligned gate GaAs MESFET with p-pocket layers for high-efficiency linear power amplifiers

This paper describes a newly developed GaAs metal semiconductor field-effect transistor (MESFET)-termed p-pocket MESFET-for use as a linear power amplifier in personal handy-phone systems. Conventional buried p-layer technology, the primary technology for microwave GaAs power MESFETs, has a drawback of low power efficiency for linear power applications. The low power efficiency of the buried p-layer MESFET is ascribed to the I-V kink which is caused by holes collected in the buried p-layer under the channel. In order to overcome this problem, we have developed the self-aligned gate p-pocket MESFET which incorporates p-layers not under the channel but under the source and drain regions. This new MESFET exhibited high transconductance and uniform threshold voltage. The problematic I-V kink was successfully removed and an improved power efficiency of 48% was achieved under bias conditions, which resulted in adjacent channel leakage power at 600-kHz offset as low as -59 dBc for 1.9-GHz /spl pi//4-shift QPSK modulated input.

High-efficiency monolithic GaAs power MESFET amplifier operating with a single low voltage supply for 1.9-GHz digital mobile communication applications

A monolithic GaAs power amplifier IC using refractory WN/sub xW self-aligned gate power MESFETs has been developed for 1.9-GHz digital mobile communication systems, such as the Japanese personal handy phone system. The power amplifier operates with high efficiency and low distortion with a single low voltage supply of 2.7-3.0 V, by virtue of small drain knee voltage, high transconductance and sufficient breakdown voltage of the power MESFET. An output power of 23.7 dBm and a high power-added efficiency of 24.2% were attained at 3 V for 1.9-GHz /spl pi4-shifted QPSK (quadrature phase shift keying) modulated input when adjacent channel leakage power was -58 dBc at 600 kHz apart.<<ETX>>

A 2K-gate GaAs gate array with a WN gate self-alignment FET process

A 2K-gate DCFL GaAs gate array has been successfully fabricated with a WN gate self-alignment GaAs MESFET process. Chip size was 4.59 mm/spl times/4.73 mm. A basic cell, consisting of one DFET and three EFETs, can be programmed as an inverter or a two or three-INPUT NOR gate by personalizing with first- and second-level interconnection and via hole masks. The I/O buffer was implemented with a large DCFL push-pull circuit. The unloaded propagation delay time was 42 ps/gate at a power dissipation of 0.5 mW/gate. The increases in delay time due to various loading capacitance were 11-ps/fan-in. 16-ps/fan-out, 59-ps/1-mm interconnection and 0.95 ps/crossover (area: 2 /spl mu/m/spl times/3 /spl mu/m). An 8/spl times/8-bit parallel multiplier was fabricated on this gate-array chip. A multiplication time of 8.5 ns was achieved at a power dissipation of about 400 mW including I/O buffers.

High efficiency, low adjacent channel leakage 2-V operation GaAs power MESFET amplifier for 1.9-GHz digital cordless phone system

A low-voltage GaAs power amplifier for 1.9-GHz digital mobile communication applications such as PHS handsets has been developed, using refractory WNx/W self-aligned gate MESFETs with p-pocket layers. This power amplifier operates with a single low 2-V supply, and an output power of 21.0 dBm, a power gain of 22.3 dB, a low dissipated current of 162.9 mA and a high power-added efficiency of 38.5% were attained with a low 600-kHz adjacent channel leakage power of -58.0 dBc for 1.9-GHz /spl pi//4-shifted QPSK modulated input.

A 42ps 2K-gate GaAs gate array

TO INCREASE speed of microelectronic systems, it is the interchip signal delay that should be reduced by maximizing the integration level. As the integration level increases, however, the development time becomes longer. The rapid development of LSIs is increasingly important because the product life cycle has been becoming shorter. A gate array approach is effective under these circumstances. Very high-speed ICs such as Si bipolar ECL logic, is no exception, and 2.5-5.0K gate gate arrays with 0.35-0.5011s loaded gate delay have been developed. However, very large power consumption, 5-8W/chip, limit their field of application. GaAs gate arrays have attracted interest as a replacement for the Si ECL gate array because of the smaller gate delay and lower power consumption. To date, several types of GaAs gate array have been reported’ ’2’3. This paper will describe a 2K-gate DCFL (Direct Coupled FET Logic) GaAs gate array with a 42ps unloaded and 215ps loaded gate delay at a power dissipation of 0.5mW/gate. An 8 x 8 b parallel multiplier has been fabricated on this chip. A multipiication time of 8.5ns was achieved at a power dissipation of 400mW, an improvement over an 8 x 8b Si ECL multiplier with custom design . The current design also consumes about 35Yo less power.

A 2-V operation RF front-end GaAs MMIC for PHS hand-set

A single 2-V operation RF front-end MMIC has been developed using three kinds of self-aligned gate MESFETs. Its transmitter block of a power amplifier with an antenna switch exhibited a power gain of 28.9 dB and a high power-added efficiency of 27.0% at 20.5-dBm output power. The receiver block of a low-noise amplifier with the antenna switch exhibits a noise figure of 3.4 dB and a gain of 11.1 dB.A single 2-V operation RF front-end MMIC has been developed using three kinds of self-aligned gate MESFETs. Its transmitter block of a power amplifier with an antenna switch exhibited a power gain of 28.9 dB and a high power-added efficiency of 27.0% at 20.5-dBm output power. The receiver block of a low-noise amplifier with the antenna switch exhibits a noise figure of 3.4 dB and a gain of 11.1 dB.

A 20 GHz 8 bit multiplexer IC implemented with 0.5 /spl mu/m WN/sub x//W-gate GaAs MESFET's

An ultrahigh-speed 8 bit multiplexer (MUX) has been developed for future-generation optical-fiber communication systems having a data rate of 20 Gb/s. This IC was fabricated using a 0.5 /spl mu/m WN/sub x//W-gate GaAs MESFET process based on optical lithography, ion implantation, and furnace annealing for good reproducibility and high throughput. The WN/sub x//W bilayer gate has a low sheet resistance, improving the circuit high frequency performance. To attain 20 GHz operation, advanced circuit techniques for the source-coupled FET logic (SCFL) were introduced. A cross coupled source-follower (CCSF) was developed mainly for the highest speed buffers to enhance the bandwidth. The first-stage T-type flip-flop was designed with optimization techniques and operated up to 21.1 GHz. >