Naoto Horiguchi

Microstructure and electrical properties of Sn nanocrystals in thin, thermally grown SiO2 layers formed via low energy ion implantation

We have developed a simple technique for fabricating Sn nanocrystals in thin thermally grown SiO2 layers using low energy ion implantation followed by thermal annealing. The formed Sn nanocrystals have excellent size and depth uniformity. Their average diameter is 4.2 nm with a standard deviation of 1.0 nm. Our experimental results clearly reveal that a stable depth of Sn exists in the SiO2 layer at about 2 nm from the SiO2/Si interface. Most of the Sn nanocrystals reside near this stable depth. The I–V characteristics of the diode structure show a clear Coulomb blockade region of 0.12 V and a Coulomb staircase at 4.2 K. A Coulomb blockade region around 0 V was observed until reaching a temperature of 77 K. The features of these nanocrystals will open up new possibilities for the creation of novel devices.

Formation of Sn nanocrystals in thin SiO2 film using low-energy ion implantation

This letter reports on a simple technique for fabricating Sn nanocrystals in thin SiO2 film using low-energy ion implantation followed by thermal annealing. These Sn nanocrystals have excellent size uniformity and position controllability. Their average diameter is 4.8 nm with a standard deviation of 1.0 nm. Most of the Sn nanocrystals reside at the same depth. The lateral edge-to-edge spacing between neighboring Sn nanocrystals is fairly constant: about 3 nm. A narrow as-implanted ion distribution profile and the effect of the SiO2–Si interface are considered to contribute to the size uniformity and position controllability. The features of these nanocrystals will open up new possibilities for novel devices.

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

Strain enhancing laminated SiN (SELS) is reported for the first time. Although the same thickness and stress SiN film is used, channel strain is enhanced by multi layer deposition. This effect was investigated by our simulations and experiments. To solve wafer bending problem, we developed a new process flow which selectively forms SELS only on the nMOS gate. A high performance 37nm gate nMOSFET and 45nm gate pMOSFET (stage IV) were demonstrated with a drive currents of 1120/spl mu/A//spl mu/m and 690/spl mu/A//spl mu/m at V/sub dd/=1V/I/sub off/=100nA//spl mu/m, respectively. This is the best drive current among the recent reports.

ELECTRON TRANSPORT PROPERTIES THROUGH INAS SELF-ASSEMBLED QUANTUM DOTS IN MODULATION DOPED STRUCTURES

We report electron transport properties through InAs self-assembled quantum dots in a modulation-doped structure with split gates. We observed drain current modulation with respect to gate voltage due to electron transport through the quantum level of InAs dots. The energy gaps estimated from the temperature dependence study of valley current and the voltage difference between the drain current peaks were consistent with each other and as large as 14 meV. The energy gaps can be explained by the charging energy of the InAs dots.

Single electron charging of Sn nanocrystals in thin SiO/sub 2/ film formed by low energy ion implantation

We report on a simple technique for fabricating a Sn nanocrystal array in thin SiO/sub 2/ film. This technique uses low energy ion implantation followed by thermal annealing. Isolated Sn nanocrystals 5 nm in diameter are formed in an array with excellent size and position uniformity. Barrier height between a Sn nanocrystal and the substrate was obtained by measuring the temperature and frequency dependence of the capacitance of the diode structure. Single electron charging effects of the Sn nanocrystals were observed from current-voltage characteristics.

Patterned self-assembly of one-dimensional arsenic particle arrays in GaAs by controlled precipitation

A process for the patterned self‐assembly of nanometer‐scale particles within a solid is described. The process uses crystal strain and composition to guide the formation of arsenic precipitates in GaAs‐based epitaxial layers grown at low temperature by molecular beam epitaxy. The lateral particle position is controlled by the strain produced by a surface stress structure while the vertical position is controlled by the epitaxial layer composition. Arsenic particles ∼16‐nm in diameter are fabricated in one‐dimensional arrays with a 23‐nm edge‐to‐edge particle spacing at a depth of 45 nm below stressors 200 nm in width, thereby demonstrating this technique.

A Direct Tunneling Memory (DTM) utilizing novel floating gate structure

A novel floating gate (FG) memory, Direct Tunneling Memory (DTM) is demonstrated. The main features of DTM are an ultra-thin tunnel oxide with leakage stop barrier and sidewall control gate (CG) which prevent the overlap between a FG and source/drain (SD) extensions. This structure suppresses the gate leakage current and improves the retention time while high speed write/erase operations with low voltage can be achieved due to the ultra-thin tunnel oxide.

Dynamic properties of InAs self-assembled quantum dots for spectral hole burning memory application

In this paper we report the dynamic properties of InAs self-assembled quantum dots for spectral hole burning memory applications. We measured the time constant of electron transport between InAs self-assembled quantum dots and the n-GaAs substrate by making use of the frequency dependence of the CV signal due to the InAs dots. We obtained a time constant of 2.1 /spl mu/s from experiments. The experimental results are well explained by equivalent circuit calculations and the theoretically calculated CR time constant. The time constant is expected to reach the sub-picosecond range in samples with a 10 nm barrier thickness.

Observation of single electron effects using HEMT

Abstract We have fabricated laterally confined quantum dots and high electron mobility transistors (HEMTs) monolithically. The HEMT gate is capacitively coupled to the quantum dot. The drain current of the HEMT is sensitive to the voltage variations caused by single electron charging in the dot. We have observed a wide variety of HEMT current oscillations which correlate with Coulomb Blockade oscillations. The amplitude of HEMT current strongly depends on the bias conditions of the tunneling barriers. In certain bias conditions, the HEMT becomes insensitive to the electron charging in the dot even though Coulomb Blockade conditions are satisfied. This property can be explained qualitatively by using a simple model.

Electron transport properties in InAs self-assembled quantum dot HEMTs

In this paper we propose InAs self-assembled quantum dot high electron mobility transistors (HEMTs) to investigate the electron transport properties in InAs self-assembled quantum dots. We measured the Vgs-Id characteristics, their temperature dependence and the Vds-Id characteristics. The experimental results show that the resonant tunneling via the quantum levels of InAs self-assembled quantum dots is modified by their charging energy.