K. Goto

Silicon (001) surface after annealing in hydrogen ambient

We investigated Si surfaces after annealing in a H2 ambient using attenuated total reflection in the infrared region, reflective high energy electron diffraction, Auger electron spectroscopy, and atomic force microscopy. We found that at all H2 pressures the surface dangling bonds formed dimers that were related to two‐domain (2×1) or c(4×2) reconstructed surfaces. H2 was adsorbed on the reconstructed surface and terminated a pair of dangling bonds that did not form dimers. H2 adsorption was limited by the reaction between H2 and the dangling bonds on the surface. The activation energy of H2 adsorption was 0.4–0.6 eV higher than that of H2 desorption. The surface on which H atoms were adsorbed and dimers were formed was inert, which kept the surface clean. We also found that the H2 annealed surfaces were influenced by surface roughness and contaminants including oxygen and carbon.

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

Strain enhancing laminated SiN (SELS) is reported for the first time. Although the same thickness and stress SiN film is used, channel strain is enhanced by multi layer deposition. This effect was investigated by our simulations and experiments. To solve wafer bending problem, we developed a new process flow which selectively forms SELS only on the nMOS gate. A high performance 37nm gate nMOSFET and 45nm gate pMOSFET (stage IV) were demonstrated with a drive currents of 1120/spl mu/A//spl mu/m and 690/spl mu/A//spl mu/m at V/sub dd/=1V/I/sub off/=100nA//spl mu/m, respectively. This is the best drive current among the recent reports.

Reduction of boron transient enhanced diffusion in silicon by low-energy cluster ion implantation

Abstract Future integrated circuits require shallow pn junctions with a depth below 50 nm and, therefore, low energy ion beams are necessary. Cluster ions can realize both goals of low-energy and high-current ion beams quite easily, because the kinetic energy of a cluster is shared among constituent atoms. Another advantage of cluster ion implantation is that the substrate damage induced by ion bombardment can be controlled by changing the cluster size. As a consequence, the transient enhanced diffusion (TED) of the dopant during annealing can be controlled in cluster ion implantation. We have used the polyatomic cluster, decaborane (B10H14) to form very shallow p+ junctions. During 900 °C annealing, the diffusion of boron atoms implanted at 3 keV was strongly suppressed compared with that implanted at 10 keV implantation. The difference in defect distribution between 10 and 3 keV implantation caused the different annealing behavior.

A new leakage mechanism of Co salicide and optimized process conditions [for CMOS]

We have clarified a new leakage mechanism in Co salicide process for the ultrashallow junctions of 0.1-/spl mu/m CMOS devices and revealed the optimum Co salicide process conditions for minimizing the leakage current. We found that leakage currents flow from many localized points that are randomly distributed in the function area. We successfully verified our localized leakage model via Monte Carlo simulation. We identified abnormal CoSi/sub x/ spikes under the Co silicide film, as being the origin of the localized leakage current. These CoSi/sub x/ spikes grow rapidly only during annealing between 400 and 450/spl deg/C for 30 s when Co/sub 2/Si phase is formed. These spikes never grow during annealing at over 500/spl deg/C, and decrease with high temperature annealing. A minimum leakage current results by optimized annealing at between 800 and 850/spl deg/C for 30 s. This is because a trade-off exists between reducing the CoSi/sub x/ spikes and preventing the Co atom diffusion from Co silicide film to Si substrate, which begins at annealing above 900/spl deg/C.

A high performance 50 nm PMOSFET using decaborane (B/sub 10/H/sub 14/) ion implantation and 2-step activation annealing process

A high performance 50 nm PMOSFET with 7-nm-deep ultra shallow junction is described. Ultra-low energy implantation of B/sub 10/H(14/sup +/) at 2 keV (effective energy of boron is 0.2 keV) which never causes transient enhanced diffusion (TED) is utilized for the extension formation. To prevent thermal diffusion (TD), we developed a 2-step activation annealing process (2-step AAP) which forms a shallow extension with a low temperature annealing after the deep source/drain (S/D) formation. The highest drive current of 0.40 mA/um (@I/sub off/ of 1 nA/um and V/sub d/=-1.8 V) which improves 15% as compared with published data is achieved. The smallest PMOSFET with a L/sub eff/ of 38 nm is demonstrated for the first time. A low S/D series resistance R/sub sd/ of 760 ohm-um is achieved even if using a high sheet resistance (>20 Kohm/sq) for the extension regions due to the diminished extension length.

Transistor-and Circuit-Design Optimization for Low-Power CMOS

CMOS-technology scaling has moved to a power-constrained condition regardless of the application segments. Power management in advanced CMOS technology drives the need to conciliate scaling-driven fundamental material limitations with product and application evolution requirements. Flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize systems on a chip. This paper reviews issues associated with transistor scaling and co-optimization for power-management circuit-design schemes for active-and leakage-power control. This paper also addresses the derived trends and implications on I/O and analog-transistor scaling.

A thermal activation view of low voltage impact ionization in MOSFETs

The authors present a thermal activation perspective for direct assessment of the low voltage impact ionization in deep-submicrometer MOSFETs. A comparison of the experimentally determined activation energy and a simple theoretical model is used to demonstrate the underlying mechanism responsible for impact ionization at low drain bias. The study indicates that the main driving force of impact ionization changes from the electric field to the lattice temperature with power-supply scaling below 1.2 V. This transition of driving force results in a linear relationship between log(I/sub SUB//I/sub D/) and V/sub D/ at sub-bandgap drain bias, as predicted by the proposed thermally-assisted impact ionization model.

21 psec switching 0.1 /spl mu/m-CMOS at room temperature using high performance Co salicide process

In this paper we report a record of 0.1 /spl mu/m-CMOS switching delay of 21 psec per gate at room temperature operation. Good subthreshold characteristics are achieved for 0.1 pm gate length n-MOS and p-MOS. Conventional Ti, Pt and Co self-aligned silicide process (salicide) degraded the 0.1 pm CMOS switching delay because the gate sheet resistances increased at fine-line. In contrast, Co salicide with TiN capping process achieved a low gate resistance of 5 /spl Omegasq at all over gate length. And it allowed the high speed operation at the sub quarter micron gate length region.<<ETX>>

A 140 GHz ft and 60 GHz fmax DTMOS integrated with high-performance SOI logic technology

We integrated an RF-nMOSFET with 130-nm SOI high-end logic technology. Using the dynamic threshold structure (DTMOS) and channel engineering, we obtained an ft of 140 GHz and an fmax of 60 GHz when Vgs=0.65 V and Vds=1.5 V, while the logic CMOS showed Ion-Ioff characteristics better than those reported for SOI-CMOS devices. The RF characteristics were analyzed using a newly developed small-signal equivalent circuit model that has an additional current source to express the body contribution of the DTMOS. These analyses revealed that channel engineering is important in improving RF performances.

Ultra-low contact resistance for deca-nm MOSFETs by laser annealing

We demonstrate an ultra-low contact resistance of 4/spl times/10/sup -8/ /spl Omega/-cm/sup 2/ (5/spl times/ lower than RTA) using a laser annealing (LA) process. The contact resistance reduction is attributed to the high activated dopant concentration of 10/sup 21/ cm/sup -3/. For the first time, we have successfully fabricated LA-pMOSFETs with a conventional CMOS integration flow for lowering contact resistance.