Naoya Azuma

In-system diagnosis of RF ICs for tolerance against on-chip in-band interferers

The tolerance of RF ICs against on-chip in-band interferers is diagnosed from the viewpoints of the quality of wireless channels compliant with LTE standards. The on-chip interferers inevitably propagate from other active circuits like digital backend processors through silicon substrate coupling in the same die of system-level integration. An in-system diagnosis platform of RF ICs presented in this paper relates the impacts of such interferers on the circuit-level response and system-level communication performance metrics. The figures of communication quality at a system level, like EVM, BER and throughput are concurrently evaluated with the strengths of interferers in different forms and at different locations in a silicon chip. The interferers are measured as the in-band signal to spurious power ratio at the output of RF ICs, the magnitude of substrate voltage fluctuations at the proximity of RF ICs, and related with the amount of power current consumed by base-band digital ICs. The tolerance of RF ICs is represented by the maximum strength of on-chip interferers for sustaining prescribed communication performance. The diagnosis system is divided into two parts, (i) a system-level RF simulator handling modulation and demodulation of real communication vectors in LTE format and also enabling hardware connectivity with RF ICs, and (ii) a silicon emulator of on-chip interferers coupled to the RF ICs. A 65 nm CMOS chip incorporates an on-chip arbitrary noise generator, an on-chip waveform capture, and RF IC for LTE receiver front end, and demonstrates the entire diagnosis.

Evaluation of environmental noise susceptibility of RF circuits using direct power injection

Susceptibility of radio frequency (RF) circuits against environmental noises was evaluated by way of direct power injection. Measurements performed on a 90-nm 2.45 GHz CMOS RF driver amplifier show that the injection of RF power into on-die p+ guard bands creates tones at the primary and up-converted frequencies. Simulation achieves the error of less than 2dB against the measured susceptibility of −40dB, with the models of passive impedance networks covering probing tips, die pads, metal wirings, as well as a silicon substrate.

Extraction of lumped RC elements representing substrate coupling of RF devices

Lumped RC elements that dominantly characterize parasitic coupling of RF devices to a silicon substrate are precisely determined from S parameters. Two-port test structures of substrate coupling were developed for a variety of geometries and dimensions of RF devices in a 65 nm CMOS technology. While the meshing of an entire test structure provides a greedy representation of a substrate coupling network and accurately captures its overall response given in S parameter, the subsequent translation with a pi-shaped model compactly attributes the substrate coupling to a few decisive RC elements at the vicinity of a device. Measurements and simulation evaluate the strengths of substrate coupling with the discrepancy of less than 3 dB from each other in the frequency range up to 8 GHz, and clearly analyze the relation of the resolved RC elements to the geometry of devices.

Emulation of high-frequency substrate noise generation in CMOS digital circuits

A noise emulator is based on the capacitor charging modeling and generates power and substrate noises expected in a CMOS digital integrated circuit. An off-chip near-magnetic-field sensor indirectly characterizes the distribution of clock timing and the adjustability of skews within on-chip digital circuits. An on-chip noise monitor captures power and substrate noise waveforms and evaluates noise frequency components in a wide frequency bandwidth. A 65 nm CMOS prototype demonstrated power and substrate noise generation in a variety of operating scenarios of digital integrated circuits. Power noise generation emulated at 125 MHz exhibits the enhancements of high-order harmonic components after deskewing at a timing resolution of 37.8 ps, as is specifically seen in more than 10 dB enlargement of the substrate noise component at 2.1 GHz.

Evaluation of substrate noise coupling in RFICs (invited)

Substrate noise coupling and impacts on RF integrated circuits (RFICs) have been intensively studied for intending a single chip solution of wireless communication systems. On-chip measurements characterize noises from digital parts of mixed-signal ICs in terms of noise generation as well as noise propagation through a silicon substrate, demonstrated by silicon results with sub-100 nm CMOS test vehicles. Simulation and emulation help further understanding of the interference of such noises with RFIC operation as well as their impacts on RF communication.