Noriyuki Miura

A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)

A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits non-return-to-zero signaling are developed. Test chips stacked at a distance of 300/spl mu/m communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35/spl mu/m CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.

A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping

A transceiver for inductive-coupling is realized. By using a pulse-shaping circuit, the transmitter energy is 0.11pj/b. Due to device scaling from 180nm CMOS to 90nm CMOS, the receiver energy is 0.03pJ/b. The overall energy dissipation is 20times lower than previous work, without degrading the data rate of 1Gb/s.

A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30mum. The total layout area is 2mm2 in 0.18mum CMOS and the chip thickness is 10mum. 4-phase TDMA reduces crosstalk and the BER is <10minus;12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link

A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 mum in a layout area of 1 mm2. The total layout area including 16 clock transceivers is 2 mm2 in 0.18 mum CMOS and the chip thickness is reduced to 10 mum. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10-13

A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package

A wireless interface by inductive coupling achieves aggregated data rate of 195 Gb/s with power dissipation of 1.2W among 4-stacked chips in a package where 195 transceivers with the data rate of 1 Gb/s/channel are arranged in 50-/spl mu/m pitch in 0.25-/spl mu/m CMOS technology. By thinning chip thickness to 10/spl mu/m, the interface communicates at distance of 15 /spl mu/m at minimum and 43 /spl mu/m at maximum. A low-power single-end transmitter achieves 55% power reduction for multiple connections. The transmit power is dynamically controlled in accordance with communication distance to reduce not only power dissipation but also crosstalk.

An 11Gb/s Inductive-Coupling Link with Burst Transmission

An inductive-coupling link is presented whose data rate is 11Gb/s for a distance of 15mum and 8.5Gb/s for a distance of 45mum. The data rate is increased by 11 to 8.5x over past inductive-coupling links. Compared with the capacitive-coupling link (Cu et al., 2007), the communication distance is extended by 5x for the same data rate, layout area, and bit error rate (BER), even by using a less- scaled device technology, 0.18mum CMOS.

A 195Gb/s 1.2W 3D-stacked inductive inter-chip wireless superconnect with transmit power control scheme

An inductively coupled wireless interface achieves aggregated data rate of 195Gbit/s among 4 stacked chips in a package by arranging 195 transceivers in 50/spl mu/m pitch with power dissipation of 1.2W. The transmit power is controlled in accordance to the communication distance to reduce both the power dissipation and the crosstalk of the system.

A High-Speed Inductive-Coupling Link With Burst Transmission

A high-speed inductive-coupling link is presented. It communicates at a data rate of 11 Gb/s for a communication distance of 15 mum in 180 nm CMOS. The data rate is 11times higher than previous inductive-coupling links. The communication distance is 5times longer than a capacitive-coupling link for the same data rate, bit error rate, and layout area. Burst transmission utilizing the high-speed inductive-coupling link is also presented. Multi-bit data links are multiplexed into a single burst data link. It reduces layout area by a factor of three in 180 nm CMOS and a factor of nine in 90 nm CMOS.

Cross talk countermeasures in inductive inter-chip wireless superconnect

Inductive coupling among stacked chips in a package enables 1.2 Gb/s/channel data communications. An array arrangement of the channel increases data bandwidth, while the signal may be degraded by cross talk. In this paper, cross talk is measured and analyzed, and cross talk countermeasures are discussed for the first time. Received signal waveforms by the inductive coupling are measured by embedded voltage detectors on a test chip. The interference-to-signal ratio (ISR) has good agreement between the measurements and calculations from a theoretical model. It is found that cross talk is reduced to being negligibly small at a certain distance. If the channels are arranged at intervals of this distance, ISR is minimized. A technique based on time division multiple access (TDMA) is also proposed to further reduce cross talk.

6W/25mm 2 inductive power transfer for non-contact wafer-level testing

Wafer-level testing allows detection of manufacturing errors and removes nonfunctional devices early in the fabrication process. It is commonly performed by placing a probe card directly above a device under test (DUT) and establishing a mechanical contact between them by means of an array of probes. This is an invasive technique that may damage fragile low-k dielectric layers and deform pads or bumps. More importantly, it is very difficult to flip thinned wafers face up for probing if they were earlier positioned face down for back grinding. Additional difficulty in handling of thinned wafers arises if dies have to be flipped again for bumping. One solution to above problems is wireless probing. With a number of proposed techniques for establishing high-speed inductive-coupling data links [3] and measuring DC analog signal wirelessly [4], the largest remaining obstacle to non-contact wafer-level testing is supplying power to the DUT. This is because wireless power transfer solutions reported earlier [1,5] do not provide an output power that is sufficient for testing modern high performance devices.