Naoyuki Kai

A 40-Mpixel/s bit block transfer graphics processor

A man-machine-interface-oriented graphics processor featuring data transfer speed of over 40 picture/s and character-front bit-mapped speed of over 15000 characters/s in a 1024*768-pixel-resolution color-CRT (cathode-ray-tube) system is discussed. The high-speed operation was attained by a memory interleaving scheme. The detailed timing for the high-speed scheme and its compactness are shown, using an actually fabricated application board. The chip layout was accomplished with a standard-cell-based approach with 1.0- mu m CMOS process. >

A high speed outline front rasterizing LSI

A description is given of a high-speed outline front rasterizing LSI, the Font Graphics Accelerator (FGA), for desktop-publishing applications. A filling algorithm that is easy to implement and assures the correct filling has been developed for the FGA. The FGA has dedicated hardware that rasterizes a Bezier curve at an average of 200 ns/dot by sequentially dividing the curve. It also has a digital difference analyzer for generating lines and arcs. Using this hardware it can generate Japanese kanji characters at an average rate of 4000 characters/s. The chip was fabricated with 1.2- μm double-metal-layer CMOS technology, and operation at 20 MHz has been achieved

Design of an outline font rasterizing LSI

lchiro Nagashima. Naoyuki Kai, Tsutomu Minagawa and Masahide Ohhashi Semiconductor Device Engineering Labratory Toshiba Corporation 580-1, Horikawa-cho, Saiwai-ku, Kawasaki, 210, Japan Phone (044)548-2511

Bit map control processor (BMCP) design

A graphic processor, featuring 320-Mb/s bit BLT (bit boundary block transfer) speed, was developed using a novel memory cycle scheme. The key to the system design is a C/Unix-based RTL simulator program, which replaced breadboard hardware. The authors describe the BMCP architecture, the design step, and the design methodology.<<ETX>>