Masahide Ohhashi

A high speed outline front rasterizing LSI

A description is given of a high-speed outline front rasterizing LSI, the Font Graphics Accelerator (FGA), for desktop-publishing applications. A filling algorithm that is easy to implement and assures the correct filling has been developed for the FGA. The FGA has dedicated hardware that rasterizes a Bezier curve at an average of 200 ns/dot by sequentially dividing the curve. It also has a digital difference analyzer for generating lines and arcs. Using this hardware it can generate Japanese kanji characters at an average rate of 4000 characters/s. The chip was fabricated with 1.2- μm double-metal-layer CMOS technology, and operation at 20 MHz has been achieved

4-µm LSI on SOS using coplanar-II process

SOS Si-gate 4-µm NMOS devices using a coplanar process (Coplanar-II process) have been investigated for the purpose of improving thé power-delay product and SOS LSI reliability. The gate breakdown field is improved by more than a factor of two (8.7 MV/cm) over that of transistors fabricated by a conventional SOS process. Two types of anomalous drain leakage currents which flow along the edge of the silicon island formed by using the conventional SOS process are suppressed. A typical drain leakage current is7 \times 10^{-11}A/8 µm. The typical values of speed and power-delay product are 0.70 ns and 0.21 pJ for 4-µm channel length devices and 0.57 ns and 0.17 pJ for 3-µm devices. These values are 1.6 times faster than that of MOS/bulk due to a lack of stray capacitance in MOS/SOS. The temperature dependence of the delay time in NMOS/SOS E/D devices can be minimized by choosing the load transistor threshold voltage (VTD) to be -2.1 V. This is attributed to the higher temperature dependence of VTDthan that of MOS/bulk. The Coplanar-II process with Si-gate 4-µm NMOS/SOS is successfully applied to the fabrication of a 1300-gate LSI, RF0 (Register File 0). The circuitry has a unique register port which can be addressed from two independent ports simultaneously. In order to obtain higher speed and lower power, four kinds of threshold voltages are used. The circuits give rise to stable operation without any timing pulse such as a precharge and a higher internal access time of 25 ns in RF0, which consists of 256-bit memory and peripheral control circuit.

A 7000-gate microprocessor on SOS—PULCE

An n-channel MOS LSI microprocessor integrating 20 000 transistors on a chip has been realized on a sapphire substrate utilizing the Coplanar-II process. It contains ALU, shifters, and 44 registers which are combined to three 16-bit buses. By utilizing three types of threshold voltage for load transistors, 28-percent reduction in power dissipation is achieved. The minimum cycle time is 200 ns. By using the Coplanar-II process, anomalous leakage currents due to parasitic transistors at the sides of island are suppressed. It is found that the silicon-on-sapphire (SOS) version operates 2.3 times faster than the bulk-silicon version, which is mainly explained by the parasitic capacitance ratio. Parallel-plate approximation in calculating a wiring capacitance results in an underestimate by a factor of 60 compared with taking the two-dimensional effect into account. It is verified that a) the observed yield of a very large SOS chip is higher than the value predicted from a randomly distributed defects model, and b) the yield-sensitive active area of an SOS is so small that it can compensate for the yield degradation due to the very large defects density on an SOS wafer.

A 2400-gate RALU on SOS

Register and arithmetic logical units on SOS have been realized by n-channel silicon gate MOS/SOS technology. The circuits are composed of enhancement drivers and depletion load transistors to implement local storage and ALU with 2400 gates, and only a +5 V power supply and a single clock are required. The circuits performances are compared with those of bulk silicon circuits. Speed power improvement of about a factor of three over bulk silicon MOS is achieved by SOS in carry propagation circuits in the ALU. The improvement is explained by (a) the reduction of capacitance of SOS by a factor of 2.5, and (b) the reduction of delay time by a factor of 1.4 by the lack of substrate bias effect. The above results clearly suggest a promissing future of SOS random logic LSI.

A 7000-gate microprocessor on SOS-PULCE

An n-channel MOS LSI microprocessor integrating 20000 transistors on a chip has been realized on a sapphire substrate utilizing the Coplanar-II process. It contains ALU, shifters, and 44 registers which are combined to three 16-bit buses. By utilizing three types of threshold voltage for load transistors, 28-percent reduction in power dissipation is achieved. The minimum cycle time is 200 ns. By using the Coplanar-II process, anomalous leakage currents due to parasitic transistors at the sides of island are suppressed. It is found that the silicon-on-sapphire (SOS) version operates 2.3 times faster than the bulk-silicon version, which is mainly explained by the parasitic capacitance ratio. Parallel-plate approximation in calculating a wiring capacitance results in an underestimate by a factor of 60 compared with taking the two-dimensional effect into account.

A 16-bit microprocessor on SOS–PULCE–

A 16-bit parallel microprocessor which contains more than 7000 gates has been realized by combining the newly developed Coplanar-II process, 4 µm channel length design rule and n-channel enhancement driver/depletion load technology on a sapphire substrate. The circuits contain 44 registers and are interconnected by the three-bus system. 28% reduction in power dissipation is achieved by utilizing three types of threshold voltage for load transistors. The cycle times are measured and compared with those for bulk silicon. High speed operation, 200 ns cycle time, is achieved with SOS version. It is 2.3 times shorter compared with bulk silicon version. A large portion of the cycle time is spent for charging up of bus lines and long control lines. It is found that the capacitance ratio of SOS/bulk silicon for bus lines is about 1/2.7.