Masato Nagamatsu

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology

A 54 b*54 b multiplier fabricated in a double-metal 0.5 mu m CMOS technology is described. The 54 b*54 b full array is adopted to complete multiplication within one latency. A 10 ns multiplication time is achieved by optimizing both the propagation time of the part consisting of 4-2 compressors and the propagation time of the final adder part. The n-channel pass-transistor circuit and the p-channel load circuit are used at the critical blocks to improve the multiplication speed. This multiplier is intended to be applied to double-precision floating-point data processing based on the IEEE standard up to clock range of 100 MHz. >

A 320 MFLOPS CMOS floating-point processing unit for superscalar processors

A CMOS pipelined floating-point processing unit (FPU) for superscalar processors is described. It is fabricated using a 0.5 mu m CMOS triple-metal-layer technology on a 61 mm/sup 2/ die. The FPU has two execution modes to meet precise scientific computations and real-time applications. It can start two FPU operations in each cycle, and this achieves a peak performance of 160 MFLOPS double or single precision with an 80 MHz clock. Furthermore, the original computation mode, twin single-precision computation, double the peak performance and delivers 320 MFLOPS single precision. Its full bypass reduces the latency of operations, including load and store, and achieves an effective throughput even in nonvectorizable computations. An out-of-order completion is provided by using a new exception prediction method and a pipeline stall technique. >

A 15-ns 32*32-b CMOS multiplier with an improved parallel structure

A high-speed 32*32-b parallel multiplier with an improved parallel structure using 0.8- mu m CMOS triple-level-metal technology is discussed. A unit adder, a 4-2 compressor, enhances the parallelism of the multiplier array. A 25% reduction in the propagation delay time is achieved by using the compressor. The multiplier contains 27704 transistors with a 2.68-*2.71-mm/sup 2/ die area. The multiplication time is 15 ns at 5 V with a power dissipation of 277 mW at 10-MHz operation. The triple-level-metal interconnection technology reduces the multiplier layout area. Compared with double-level-metal technology, a 27% chip size reduction is achieved. >

A 40-Mpixel/s bit block transfer graphics processor

A man-machine-interface-oriented graphics processor featuring data transfer speed of over 40 picture/s and character-front bit-mapped speed of over 15000 characters/s in a 1024*768-pixel-resolution color-CRT (cathode-ray-tube) system is discussed. The high-speed operation was attained by a memory interleaving scheme. The detailed timing for the high-speed scheme and its compactness are shown, using an actually fabricated application board. The chip layout was accomplished with a standard-cell-based approach with 1.0- mu m CMOS process. >

A 15 ns 32atimes;32-bit CMOS multiplier with an improved parallel structure

A 32-bit×32-bit parallel multiplier with an improved parallel structure has been fabricated by 0.8-μm CMOS triple-level-metal interconnection technology. A unit adder that can sum four partial products concurrently has been developed. It enhances the parallelism of multiplier. The chip contains 27704 transistors with 2.68×2.71-mm2 die area. The multiplication time is 15 ns at 5-V power supply. The power dissipation is 277 mW at 10-MHz operation

A 10 ns 54atimes;54-bit parallel structured full array multiplier with 0.5 amu;m CMOS technology

A 54-b×54-b multiplier fabricated in double metal 0.5-μm CMOS technology is described. A 10-ns multiplication time has been achieved by employing a 4-2 compressor, a carry select adder, and a carry lookahead adder. The 54-b×54-b full array is adopted to complete the multiplication within one latency. This multiplier is intended for double-precision floating-point data processing based on IEEE standards up to a clock range of 100 MHz. The multiplier has integrated 81600 transistors in an active area of 3.62 mm×3.45 mm

Embedded memory design for a four issue superscaler RISC microprocessor

Design of embedded memories for a 64 bit superscaler RISC microprocessor is described. Since the microprocessor issues four instructions per cycle including two memory operations at a time, very wide bandwidth of the primary caches (2.4 GB/sec) is vital. The chip includes 16 KB instruction cache, 2 KB branch cache, 16 KB dual ported data cache and 384 entry dual ported TLB. Unique scheme of TLB hit check greatly reduces critical path. The chip is fabricated in Toshibas high-speed 0.8 /spl mu/m CMOS technology utilizing triple metal and triple well. The die size is 17.3 mm/spl times/17.3 mm and contains 2.6 million transistors. The chip achieves 75 MHz at 70/spl deg/C and 3.1 V.<<ETX>>