Naoyuki Ohse

High Performance SiC IEMOSFET/SBD Module

SiC power module with low loss and high reliability was developed by utilizing IEMOSFET and SBD. The IEMOSFET is the SiC MOSFET with high channel mobility in which the channel region is the p-type carbon-face epitaxial layer with low acceptor concentration. Elemental technologies for the high channel mobility and the high reliability of the gate oxide have been developed to realize the excellent characteristics by the IEMOSFET. The SBD was designed so as to minimize the forward voltage drops and the reverse leakage current. For the fabrication of these SiC power devices, the mass production technology such as gate oxidation, ion implantation and following activation annealing have been also developed.

13-kV, 20-A 4H-SiC PiN Diodes for Power System Applications

We successfully fabricated 13-kV, 20-A, 8 mm × 8 mm, drift-free 4H-SiC PiN diodes. The fabricated diodes exhibited breakdown voltages that exceeded 13 kV, a forward voltage drop of 4.9–5.3 V, and an on-resistance (RonAactive) of 12 mW·cm2. The blocking yield at 10 kV on a 3-in wafer exceeded 90%. We investigated failed devices using Candela defect maps and light-emission images and found that a few devices failed because of large defects on the chip. We also demonstrated that the fabricated diodes can be used in conducting high-voltage and high-current switching tests.

3300V-Class 4H SiC Implantation-Epitaxial Mosfets with Low Specific On-Resistance of 11.6mΩcm2 and High Avalanche Withstanding Capability

In this paper, newly developed 3300V-class IEMOSFETs were presented. By means of the optimization of current spreading layers (CSLs), we could achieve low specific on-resistance (RONA) of 11.6mΩcm2, while maintaining high blocking voltage (BVDSS) of 3978V. The RONA analysis revealed drastic reduction of JFET resistance compared to a MOSFET without a CSL. High ruggedness with the avalanche withstanding energy of 4.6J/cm2 was achieved by the optimal device design of the edge termination. We could also confirm favorable characteristics of RONA, BVDSS and threshold voltage (VTH) at high temperatures up to 200○C, and the fast switching behavior.

1200 V SiC IE-UMOSFET with low on-resistance and high threshold voltage

A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mWcm2 with a high Vth of 5.9 V.

Distribution of Secondary Defects and Electrical Activation after Annealing of Al-Implanted SiC

We investigated the relationship between secondary defects and electrical characteristics in the activation annealing (1600 °C-1800 °C) of 4H-SiC after Al implantation (3 × 1017 cm-3-3 × 1019 cm-3). X-ray topography revealed that the dislocation density did not increase after implantation and annealing. Scanning transmission electron microscopy (STEM) images revealed black spots that aggregate with increase in Al dose. The results of energy dispersive X-ray spectroscopy analysis suggested that these black spots are due to the strain of secondary defects. The I-V characteristics at reverse bias of a pin diode fabricated with Al implantation show that secondary defects shown as black spots in the STEM images do not affect the electrical characteristics under the implantation and annealing conditions used in this experiment.

Effect of Ion Implantation-Induced Defects on Leakage Current Characteristics of IEMOS

We investigated the relationship between ion implantation-induced defects and electrical characteristics, especially focusing on the leak failure rate in SiC IEMOSs and PN diodes. It was found that dislocation exists in each leakage point by analyzing identical leak-failed IEMOS by emission microscopy and refraction X-ray topography. The leak failure rate of the PN diodes and IEMOS was improved with an increase in the ion implantation temperature under the implantation and annealing conditions used in this experiment. It is considered that ion implantation-induced defects lead to an increase in leak failure rates, and also enable a decrease in leak failure rates by raising the implantation temperature up to 600 deg.C.

Improved Simulation Models for Designing Novel Edge Termination and Current Spreading Layers for 3300-V-Class 4H-SiC Implantation–Epitaxial MOSFETs with Low On-Resistance and Robustness

Impact ionization coefficients are important material properties that determine the breakdown voltage and safe operating area of power devices. This paper presents an anisotropy breakdown model with modified parameters that reproduces well experimental results for both peak breakdown voltages and sharp drops in breakdown voltage at high junction–termination–extension (JTE) acceptor concentrations. Using a newly developed simulation model, we optimized the edge termination and current-spreading layers (CSLs) and obtained a low specific on-resistance (RONA) of 11.6 mΩcm2 for a breakdown voltage (BVDSS) of approximately 4 kV and a high-avalanche-withstanding energy robustness of 4.6 Jcm-2.

Development of ultrahigh voltage SiC power devices

Ultrahigh voltage SiC devices and their package technology were investigated. As a result, we have succeeded in creating a 13kV level PiN diode without forward voltage degradation by using 4° off substrates and a 15kV level p-channel IGBT and 16kV level n-channel IGBT with a low differential specific on-resistance (Rdiff,on). Moreover, the results reveal that the nano-tech resin, improved resin and Si3N4 DBC substrate are the best materials for package at high temperature and ultrahigh voltage.