Nathan Belk

Integration of high-Q inductors in a latch-up resistant CMOS technology

Inductors fabricated using CMOS technologies based on epi/p/sup +/ substrates are severely degraded because of eddy current losses in the substrate. We propose and demonstrate a modified substrate structure, which addresses the conflicting goals of high inductor quality-factor and high latch-up immunity. Results include fabricated inductors with Q-factor as high as 16.

Design, test, and simulation of self-assembled micromachined rf inductors

Inductors are essential for fully integrated, complex RF circuits such as single chip radios. Both high Q, Q > 15, and high precision, +/- 2 percent, inductors are needed to meet phase noise specifications for on-chip VCOs and for reactive impedance matching to improve power transfer and linearity. We describe the design, test and simulation of self-assembled, micromachined inductors lifted away from the substrate by tensile stress in the metallization. The air gap reduces the capacitive coupling to the substrate, increasing both the Q and self-resonant frequency. For 2nH inductors we have measured Q-14 at 2GHz, with process variation < 2 percent. Increased temperature and current strongly increase the loss, but do not effect the inductance. The inductors are also relatively insensitive to mechanical excitation, with forces approximately 30gs required to significantly modulate the inductor loss under resonant excitation. Extensive EM simulations of this design methodology suggest that we should be able to reach Q > 25 at 2GHz and maintain 10GHz. We also compare these results with state of the art fully integrated Si RFIC planar inductors.