Nathan Jack

Predictive simulation of CDM events to study effects of package, substrate resistivity and placement of ESD protection circuits on reliability of integrated circuits

Power domain crossing circuits, also known as internal I/Os, are susceptible to gate oxide damage during charged device model (CDM) events. Circuit-level simulations of internal I/O circuits along with elements representing the package, electro-static discharge (ESD) circuits and the substrate, elucidate the roles of the package, power clamp placement, back-to-back diode placement and the decoupling capacitors in determining the amount of stress at the internal I/O circuits. This paper presents an internal I/O model that can be used for CDM simulations. The effects of power and ground bus resistance, substrate resistivity, decoupling capacitance, local ESD clamp at the gate of the receiver and the presence of local back-to-back diodes are investigated. The paper further contains design recommendations for preventing CDM failures in the internal I/O circuits.

CDM-ESD induced damage in components using stacked-die packaging

CDM-ESD robustness of stacked-die packages is investigated and compared with single-die packages. The peak discharge current is not increased significantly by die stacking. The inter-die signal interfaces are shown to be well protected against CDM by placing just a small ESD protection clamp at the receiver, if certain package integration guidelines are followed.

ESD protection for high-speed receiver circuits

ESD-induced gate oxide breakdown is studied in high-speed receiver circuits. A novel biasing circuit increases the breakdown voltage by modulating the potential of the input transistors source during ESD. The effectiveness of dual-diode and DTSCR protection of high-speed receiver circuits is examined under various bias conditions.

Comparison of FICDM and Wafer-Level CDM Test Methods

The on-chip stresses induced by various charged device model (CDM) test methods are compared at both the package and wafer levels. Test methods studied include field-induced CDM (FICDM), wafer-level CDM (WCDM2), capacitively coupled transmission-line pulsing (CC-TLP), and very fast TLP (VF-TLP). The generated stresses are compared on the basis of voltage monitor readings and integrated circuit (IC) functional failures. In general, core circuit failures induced by FICDM are replicated on the wafer level. Package-related parasitics can alter the externally measured FICDM current pulse relative to that delivered internal to the IC, causing miscorrelation with wafer-level testers.

Exponential-edge transmission line pulsing for snap-back device characterization

A new ESD testing system, the exponential-edge transmission line pulse system (EETLP), is presented. EETLP generates 100ns square pulses with a variable, exponentially decaying falling edge. When applied to an ESD protection device, the pulse shape allows for capture of both the transient and quasi-steady-state responses, in the context of a single measurement. EETLP provides unprecedented insight into the turn-off dynamics of snapback-type devices. Device measurement data are presented to demonstrate the capabilities of EETLP.

Comparison of Wafer-Level With Package-Level CDM Stress Facilitated by Real-Time Probing

Using real-time voltage probing and circuit simulation, the stress induced by wafer-level charged-device-model (CDM) electrostatic discharge test methods is compared to that of package-level field-induced CDM testers. It is shown that, while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.

WCDM2 — Wafer-level charged device model testing with high repeatability

CDM-like unipolar pulses are generated at the wafer level with excellent repeatability and linearity. Pulse width and rise time resemble that of FICDM testers. In-situ pre- and post-stress curve tracing reveals the current failure threshold for the device under test.