Bruce Chou

Ultra-miniaturized and surface-mountable glass-based 3D IPAC packages for RF modules

This paper demonstrates ultra-miniaturized RF passive components integrated on thin glass substrate with small Through Package Vias (TPVs) to realize 3D Integrated Passive and Actives Component (IPAC) concept. Miniaturization is achieved through; a) ultra-thin glass, b) low-loss thin dielectrics and c) small TPVs. Inductors, capacitors and low pass filters functioning in the frequency range of 0.8 GHz to 5.4 GHz were modeled and fabricated between thin dielectric layers on 100 μm thin glass, and then assembled on PCB through BGA interconnections. The simulated results corroborated well with measured results, providing guidelines for RF module fabrication.

Modeling, design, and fabrication of ultra-high bandwidth 3D Glass Photonics (3DGP) in glass interposers

This paper presents, for the first time, the 3D Glass Photonics (3DGP) technology being developed by Georgia Tech, based on ultra-thin 3D glass interposer [1]. The 3DGP system integrates both optical and electrical interconnects in the same glass substrate using photo-sensitive polymer core, and polymer cladding within an ultra-thin glass substrate. The 3DGP processes are demonstrated using 180 & 100 um thick glass substrates with 30 um diameter via and 8 um wide waveguide structures. The optical vias are used as mode transformer and high-tolerance coupler between fibers and chips. Finite-difference analysis is performed to determine the alignment tolerances of such vias.

Design and Demonstration of 2.5D Glass Interposers as a Superior Alternative to Silicon Interposers for 28 Gbps Signal Transmission

This paper presents the design and demonstration of redistribution layers directly on the surface of glass for highspeed 28 Gbps signaling applications. An unprecedented demand for bandwidth to support cloud and edge computing driven by online services is expected with the continued proliferation of connected devices including smartphones, Internet of Things, and autonomous electric vehicles. High performance systems supporting electrical signal speeds up to and beyond 28 Gbps are required, thus driving the development of advanced multi-chip architectures such as 2.5D interposers. Silicon interposers have been developed and manufactured, but are limited in performance and cost. High conductor and dielectric losses limit maximum data rate, while 300 mm wafer size and expensive damascene processes increase packaging costs. Glass interposers provide similar interconnect densities as silicon but at higher performance and lower cost. The smooth surface roughness (Ra <; 10 nm) and low total thickness variation of glass enables fine pitch panel lithography approaching back-end-of-line design rules, while the lower loss tangent of glass and thicker copper metallization reduces dielectric and conductor losses respectively. This work describes the design and demonstration of differential, high-speed traces on a two-metal layer glass interposer. These redistribution layers were fabricated using panel-scalable, semi-additive processes and characterized up to f = 40 GHz using on-panel calibration. Differential crosstalk below 30 dB up to f = 40 GHz was demonstrated without ground shielding at a differential pair spacing greater than 200 μm.

Modeling, design, and demonstration of 2.5D glass interposers for 16-channel 28 Gbps signaling applications

This paper describes the modeling, design, and demonstration of high-speed differential transmission lines on a 130μm thin glass interposer with two re-distribution layers (RDL), line lengths of 1-50mm, and turn radii of 0.15-8mm for 16-channel signal transmission at 28 Gbps per channel. Next generation photonic systems such as 400 Gigabit Ethernet (400 GbE) require low power and low loss channels between photodetectors and trans-impedance amplifiers (TIA) or between laser arrays and driver ICs. Glass, with low dielectric constant and loss tangent, has higher electrical performance and channel power efficiency compared to silicon interposers. Furthermore, low surface roughness and high-dimensional stability of glass enable finer lithographic dimensions and higher interconnection density during large panel processing compared to organic interposers. Interconnection of optical and electrical ICs on 2.5D glass interposers provides the best combination of electrical and optical signal performance. For 400 GbE modules, a 16-channel bus at 28 Gbps per channel is required for communication to the backplane. Electrical modeling and simulation was performed to arrive at an appropriate design for the 16×28 Gbps I/O interface on a two-metal layer glass interposer. An ultra-thin 130μm glass interposer was fabricated using low-cost, double-side panel processing providing for a lower cost, higher performance solution compared to silicon interposers.

Modeling, design, and demonstration of ultra-miniaturized and high efficiency 3D glass photonic modules

This paper presents the modeling, design, and demonstration of an ultra-miniaturized 2.5D optical transceiver module using ultra-thin glass interposers with electrical and optical through vias. The 3D Glass Photonics (3DGP) technology with double sided attach of electrical and photonics ICs can achieve ultra-high bandwidth with improved power efficiency at lower cost than other photonic integration such as silicon photonics and organic boards. Thin glass substrates with 60um diameter through vias were fabricated with copper plated electrical vias and polymer-filled optical vias, formed simultaneously. Re-distribution layers were fabricated on top of these integrated vias for electrical interconnections. The 2.5D optical module produced this way features flip-chip bonded VCSEL and driver chips. Initial measurements of the optical vias showed 1.2 dB of loss.

Design and Demonstration of Micro-Mirrors and Lenses for Low Loss and Low Cost Single-Mode Fiber Coupling in 3D Glass Photonic Interposers

This paper presents the first demonstration of a novel fiber coupling structure that enables low-loss and low-cost fiber coupling in an ultra-miniaturized 3D glass photonic interposer. The novel 3D coupling structure consists of a tapered optical waveguide with an integrated lensed turning mirror on one end and a cylindrical lens on the other end, in a 150 μm glass substrate. The lens waveguide and turning mirror provide coupling loss of <;0.5 dB and 90% tolerance of 2 μm for out-of-plane coupling between a Photonic Integrated Circuit and a single-mode fiber. The lens waveguide is fabricated using planar lithography to reduce overall cost. In addition, precision U-grooves in glass are employed to allow for a coefficient of thermal expansion matched interface between the fiber and the substrate, thus enabling low-cost passive alignment.

Novel copper metallization schemes on ultra-thin, bare glass interposers with through-vias

Metallizing ultra-thin glass interposer with through-vias with high adhesion and at low cost is one of the primary challenges in producing next-generation glass-based system packages. This paper describes and investigates a new approach towards creating a glass interposer structure with through-vias that is ready for solution-based metallization such as electroless deposition. Starting with glass containing through-vias, a thin polymer film (primer) is laminated, covering the entire surface. The film is then opened over the vias, resulting in a structure that is ready for electroless deposition and is known to be thermo-mechanically reliable. The versatility and feasibility of this approach are demonstrated through the use of various primer film materials and primer opening processes. Daisy-chain reliability structures were fabricated on glass interposers metallized by this approach and electrical measurements showed expected behavior.

Design, Demonstration and Characterization of Ultra-Thin Low-Warpage Glass BGA Packages for Smart Mobile Application Processor

This paper presents the design, fabrication, assembly, and characterization of a fully-integrated single-chip glass BGA package at 40/80 μm off-chip I/O pitch with multilayered wiring and through-package-vias (TPVs) at 160 μm pitch. The designed test vehicle emulates an application processor package for smart mobile applications, and enables for the first time measurements of DC signal transmission from the die to the board, through the package, at this density and pitch. A daisy chain test die, 10 mm × 10 mm in size, was designed to emulate a logic processor chip comprising 5448 I/Os distributed in four peripheral rows at 40/80 μm pitch and a central area array at 150 μm pitch. The test dies were fabricated and bumped with standard Cu pillars by ASE. The glass package design included four routing layers, with blind vias (BVs) and TPVs both at 150 μm pitch, to connect 176 I/Os to the board, with BGAs at 400μm pitch. Independent multi-level test structures were added for evaluation of TPV and BV yield during fabrication, as well as partial chip-and board-level interconnection yield and reliability. The TPVs in glass were achieved by a via-first process with a high-throughput plasma etching and primer drilling method. Semi-additive processes (SAP), combined with wet chemical surface treatment methods were applied for patterning of the multi-layer wiring with a minimum of 20 μm Cu trace width at 40 μm pitch. A fan-in fan-out finger design was implemented on the top layer for bump-on-trace chip-level interconnections. Chip assembly on glass panels was carried out by high-speed thermocompression bonding with non-conductive paste (TC-NCP) with the new high-performance APAMA chip-to-substrate (C2S) bonder by Kulicke and Soffa. Yield of each process step was evaluated through fabrication and assembly by DC electrical characterization of TPV, BV and chip-level interconnection daisy chains. Die-to-substrate interconnections were characterized, demonstrating signal transmission through the fully-integrated glass package for the first time at this I/O pitch.

Self-aligned chip-to-chip optical interconnections in ultra-thin 3D glass interposers

This paper presents the modeling, design and demonstration of a three-dimensional polymer waveguide (3D WG) that couples two optical through-package vias (TPVs) in a 3D ultra-thin glass interposer for chip-to-chip optical communications. Coupling of the device is enabled using positive and negative sloped, 45° total internal reflection (TIR) micro-mirrors. The simulated coupling efficiency is within 0.5 dB for 45±5°. A novel inclined UV photolithography process is proposed to fabricate the microstructures simultaneously with self-alignment. The alignment is inherent because it is resolved prior to inclined photolithography during the planar patterning of double-sided metallization layers. The new process is experimentally demonstrated using commercially available PCB manufacturing technologies. The measured alignment tolerance between the optical via and the polymer waveguide is within 2.5 um across the entire panel. Fifty micron tall polymer WGs at 20 ~ 60 um width with 45 degree entry and exit turning surfaces are fabricated on 150um thick glass substrate. Rounded waveguide sidewalls and inadequate adhesion are observed, which requires further process development to allow high quality optical measurements.

Ultra-thin and ultra-small 3D double-side glass power modules with advanced inductors and capacitors

This paper demonstrates 3D functional modules that are ultra-miniaturized, high-performance and low-cost, based on an innovative 3D Integrated Passive and Active Component (3D IPAC) concept [1]. The 3D IPAC concept utilizes an ultra-thin (30-100 microns) and ultra-low-loss glass substrate, low-cost through-package-vias (TPVs) and double-side redistribution layers (RDL) for assembly of both active and passive components. In this concept, both active and passive components are integrated on both sides of the glass substrate, either as thinfilms or as discretely fabricated and assembled components, separated by only about 50-100 microns in interconnection length. This paper specifically addresses the power functional modules with passive components by integrating ultra-thin high-density capacitors on one side and power-supply inductors on the other side. The first part of the paper describes the electrical modeling and design of power inductors and capacitors in 3D IPAC structure. The second section describes the fabrication for both the building block L and C components and the assembly of integrated modules. The last section presents the electrical characterization. The paper, thus, provides a first demonstration of a novel power module platform for double-side thin active and passive component integration for power module applications.