Nathaniel Peachey

A novel on-chip protection circuit for RFICs implemented in D-mode pHEMT technology

This paper presents development of novel circuitry that protects circuits developed in pHEMT technology with minimal impact on RF performance. Reduced on-state resistance, low parasitic capacitance, variable trigger voltage, and small physical size allow the protection circuit to be an attractive solution for ESD protection. Implementation of the circuit in a wideband low noise amplifier (LNA) is presented.

A Novel Clamp Based ESD Protection Structure for High Power RF Ports in GaAs pHEMT Process

The article presents a novel method of protecting RF ports designed to handle high (>30dBm) power levels. An Enhancement mode (E-mode) pHEMT clamp consists of Field effect transistor (FET) with a resistor connected between gate and source. Our design consists of two such clamps connected in back to back configuration. The structure was connected to the Transmit (TX) port of a WiFi front end module (WiFi FEM). Transmission line pulsing (TLP) and Human Body Model (HBM) testing was used to characterize the clamp. The low capacitance (<100fF) along with high trigger voltage (±21V) makes this clamp a suitable candidate for protecting high power RF ports.

ESD power clamp with adjustable trigger voltage for RF power amplifier integrated circuit

An ESD clamp with adjustable trigger voltage for RF power amplifiers in SiGe BiCMOS is presented. A voltage divider network determines the clamp trigger voltage. The design uses a latch for a robust clamp, with a fast response time to an ESD event. Experimental data show that the trigger voltage is adjustable by changing the value of a resistor.

Robust ESD clamp for Envelop Tracking power supply

An ESD clamp intended for Envelop Tracking applications is presented. The clamp uses a reliable trigger mechanism to turn the clamp on during an ESD event. Important clamp features are immunity to voltage spikes in the power supply and a reliable power up operation. The clamp design has been validated with experimental data.

Characterization and modeling of ESD diodes in RF circuits

This paper presents the characterization of diode arrays fabricated in IBMs 0.18um CSOI7RF technology under both ESD and Radio Frequency (RF) test conditions. For the ESD characterization, HBM and TLP measurements and simulations are conducted and discussed in detail. For the RF characterization, the small signal and large signal responses are both measured and simulated. The primary focus is the diode array loading capacitance which is extracted from the small signal S-Parameters, and the harmonic power which is measured at both even and odd harmonics during a 900MHz power sweep. This research focuses on the connection between asymmetry in the diode structures (mismatch) and the even harmonic responses of bi-directional shunted ESD diode connected circuits.