Nattapol Damrongplasit

Study of Random Dopant Fluctuation Effects in Germanium-Source Tunnel FETs

The effects of random dopant fluctuations (RDFs) on the performance of Germanium-source tunnel field-effect transistors (TFETs) is studied using 3-D device simulation. The RDF in the source region is found to have the most impact on threshold voltage variation (σ<i>V</i>_TH) if the source is moderately doped (10¹⁹ cm^-3) such that vertical tunneling within the source is dominant. If the source is heavily doped (10²⁰ cm^-3) such that lateral tunneling from the source to the channel is dominant, the impact of RDF in the channel region is also significant. RDF-induced threshold voltage variation (σ<i>V</i>_TH) for an optimally designed Ge-source TFET is relatively modest (σ<i>V</i>_TH <; 20 mV at <i>Lg</i> = 30 nm), compared with a MOSFET of similar gate length. Supply voltage scaling is not beneficial for reducing TFET σ<i>V</i>_TH.

Study of Random Dopant Fluctuation Induced Variability in the Raised-Ge-Source TFET

The impact of random dopant fluctuations (RDF) on the performance of an optimized TFET design comprising a raised germanium (Ge) source region is investigated via 3-D TCAD simulation. The RDF within the source region results in degraded subthreshold swing and lower turn-on voltage for the raised-Ge-source TFET design. In addition, drain-induced barrier tunneling is mitigated with the raised source design. An optimized raised-Ge-source TFET is projected to provide for lower energy operation at frequencies up to 500 MHz when compared with an ideal MOSFET.

Variation Study of the Planar Ground-Plane Bulk MOSFET, SOI FinFET, and Trigate Bulk MOSFET Designs

The impact of systematic and random variations on transistor performance is investigated for the trigate bulk MOSFET, the planar ground-plane bulk MOSFET, and SOI FinFET. The results indicate that the trigate bulk MOSFET design is least sensitive to process-induced variations and offers the best nominal performance, as compared with the planar ground-plane bulk MOSFET and SOI FinFET.

Performance and Yield Benefits of Quasi-Planar Bulk CMOS Technology for 6-T SRAM at the 22-nm Node

The performance and threshold voltage variability of quasi-planar bulk MOSFETs are compared against those of conventional bulk MOSFETs, via three-dimensional (3-D) device simulations with gate line-edge roughness and atomistic doping profiles, at 25 nm gate length. The nominal performance of six transistor (6-T) SRAM cells is studied via 3-D simulation of full cell structures. Compact (analytical) modeling is used to estimate SRAM cell yields. As compared to conventional bulk CMOS technology, quasi-planar bulk CMOS technology provides for enhanced SRAM cell performance and yield, and hence facilitates reductions in cell area and operating voltage. It also enables a notchless 6-T SRAM cell design which is advantageous for improved lithographic printability and either smaller area or lower standby power, and is projected to achieve 6-sigma cell yields at operating voltages down to ~0.8 V.

Comparative Study of Uniform Versus Supersteep Retrograde MOSFET Channel Doping and Implications for 6-T SRAM Yield

The benefit of supersteep retrograde (SSR) channel doping for suppressing short-channel effects in planar bulk MOSFET performance is studied via technology computer-aided design simulation of devices with gate length Lg = 28 nm. It is found that drain-induced barrier lowering is reduced by more than 40%, and variation in saturation threshold voltage (σ VT,Sat), caused by random dopant fluctuation, is reduced by ~50%, with SSR channel doping. However, degraded drive current is observed for SSR channel doping due to enhanced body effect. Estimations of six-transistor static random access memory (SRAM) cell yield indicate that 33% reduction in the minimum operating voltage (VMIN,SRAM) can be achieved with SSR channel doping.

Design of Gate-All-Around Silicon MOSFETs for 6-T SRAM Area Efficiency and Yield

Gate-all-around (GAA) MOSFETs relevant for the 11.9-nm CMOS technology node are optimized with device dimensions following the scale length rule. Variability in transistor performance due to systematic and random variations is estimated with the aid of TCAD 3-D device simulations, for these well-tempered GAA structures. The tradeoff between read stability and write-ability of 6-T static RAM cell designs implemented with GAA MOSFETs with either square or rectangular nanowire channel regions is then investigated, and a calibrated transistor I-V compact model is used to estimate cell yield. The results indicate that a rectangular (thin and wide) channel design achieves the optimal balance between the read yield and write yield and hence provides for the lowest minimum cell operating voltage, estimated to be ~0.45 V, as well as smaller cell area.

4H-SiC N-Channel JFET for Operation in High-Temperature Environments

Lateral depletion-mode 4H-SiC n-channel junction field-effect transistors (JFETs) are demonstrated to operate with well-behaved electrical characteristics at temperatures up to 600°C in air. Ti/Ni/TiW metal stacks are used to form ohmic contacts to n-type 4H-SiC with specific contact resistance of 1.14 × 10^-3 Ω cm² at 600°C. The on/off drain saturation current ratio and intrinsic gain at 600°C are 1.53 × 10³ and 57.2, respectively. These results indicate that 4H-SiC JFETs can be used for extremely-high-temperature electronics applications.

Simultaneous carrier transport enhancement and variability reduction in Si MOSFETs by insertion of partial monolayers of oxygen

We demonstrate simultaneous NMOS and PMOS high-field mobility enhancement and variability reduction by inserting partial monolayers of oxygen during silicon epitaxy of the channel layer.

Extension of Planar Bulk n-Channel MOSFET Scaling With Oxygen Insertion Technology

An experimental and simulation study of short-channel planar bulk nMOSFET performance enhancement achieved with oxygen insertion technology is presented. The benefits of this technology for low-power digital logic circuits make it a promising evolutionary approach to extend bulk MOSFET scaling.

6-T SRAM cell design with gate-all-around silicon nanowire MOSFETs

6T-SRAM cell design with gate-all-around (GAA) silicon nanowire (NW) MOSFETs is investigated via three-dimensional TCAD simulations and compact analytical modeling. A rectangular NW channel design allows the transistor width to be adjusted with reduced impact on short-channel effects. This in turn provides a means for tuning the cell ratios to optimize the tradeoff between static noise margin and writeability with optimal cell layout area efficiency.