Neelofer Afzal

Digitally programmable current-conveyor based mixed-mode universal filter

This paper presents a novel mixed-mode universal filter (UF) using digitally programmable second-generation current conveyor. The proposed single filter configuration is capable of realising all the standard filter functions in both inverting and non-inverting forms in all the four modes, namely voltage mode, current mode, trans-impedance mode and trans-admittance mode. The proposed configuration provides advantageous features, such as independently programmable filter parameters, easy cascadability and low-sensitivity figures. Workability of proposed circuit is verified by including the SPICE simulations.

Fully Digitally Programmable Generalized Mixed Mode Universal Filter Configuration

This paper presents five feature-enriched hardware-efficient mixed mode universal filter (UF) biquads using digitally programmable (DP) current conveyors (CC). Common features of proposed UFs include use of only two grounded capacitors, operation in all the four modes, realization of all the filter functions, independently programmable filter parameters and cascadability (last three features, however, are partially present in last UF). Besides all these features, the first proposed UF, designated as Generalized DPUF provides additional features such as reconfigurability, use of minimum input terminals, no component matching constraint and lesser parasitic effects. Although Generalized DPUF encompasses almost all the desirable features of any filter, it uses eight CCs for obtaining these. The need of eight CCs is justified by introducing remaining four programmable/non-programmable UFs. These additional UFs are designated as Derived UFs as they are obtained by the deletion of CCs of the Generalized DPUF. Proportionate reduction in features of Derived UFs with number of CCs proves the reasonability of eight CCs in Generalized DPUF. To further strengthen this fact, all the proposed UFs are compared with reported filters. Better/comparable performance of Generalized and reduced-performance Derived filters again justifies the need of eight CCs in Generalized UF.

On advance towards sub-sampling technique in phase locked loops – A review

Abstract This paper presents a symmetric review of academic and accomplished research endeavors in the field of Sub-Sampling Phase Locked Loop (SSPLL) design. Adequate emphasis has been given to understand the yearn for development of Sub-Sampling PLLs. Techniques that have emerged over the recent few years in context of better FOM, Jitter and Phase Noise reduction while maintaining extraordinary circuit performance in Sub-Sampling PLLs with CMOS/VLSI technology, have been captured in this paper. Consecutively, the main inspiration of this study is to present an overview of the PLL fundamentals, furtherance from analog to Digital PLL and various noises encountered in the different PLL components, important for the reader to have a better understanding about the design and analysis of Sub-Sampling PLLs.

Reconfigurable Mixed Mode Universal Filter

This paper presents a novel mixed mode universal filter configuration capable of working in voltage and transimpedance mode. The proposed single filter configuration can be reconfigured digitally to realize all the five second order filter functions (types) at single output port. Other salient features of proposed configuration include independently programmable filter parameters, full cascadability, and low sensitivity figure. However, all these features are provided at the cost of quite large number of active elements. It needs three digitally programmable current feedback amplifiers and three digitally programmable current conveyors. Use of six active elements is justified by introducing three additional reduced hardware mixed mode universal filter configurations and its comparison with reported filters.

Low-Voltage Low-Power FGMOS-Based Current Conveyor III

A new realization of high-performance third-generation current conveyor (CCIII) is proposed in this paper. FGMOS technique is utilized to implement low-voltage CCIII. The inherited features of the proposed block are low supply-voltage, low-power dissipation, and high-output impedance at terminal Z. The circuit is simulated in SPICE using 0.13 µm CMOS technology.

Low frequency digitally programmable universal filter for communication system

This paper presents a low frequency digitally programmable voltage mode universal filter for modern communication systems. It employs four digitally programmable second generation current conveyors (DPCCII), two grounded capacitor and five resistors. The proposed circuit offers the features such as realization of all the standard filter functions from same configuration, independent digital control of filter parameters, no component matching constraint and low sensitivity figure. SPICE simulation results are demonstrated to confirm the theoretical analysis.

CMOS digitally programmable grounded inductor

A CMOS digitally programmable lossless grounded inductor is presented in this paper. It uses two digitally programmable second generation current conveyors (DPCCII) and three grounded passive elements including one capacitor only. The inductance value is tuned by programmable gain factor of current conveyor. As an application, a current mode multifunction filter has been realized using proposed programmable inductor. The simulation results have been demonstrated and discussed using a SPICE simulation.

Advances in sensor networks using analog signal processing circuits

With the advent in technology, wireless sensor networks are used to gather information and monitor data in the inaccessible and remote areas where wired network is not feasible. Due to limited power back-up, sensor network cannot be deployed on wider scale. Processing is recommended within network to reduce communication overhead and energy consumption. Low power analog processing circuits integrated within sensor nodes are suitable for this task. This paper reviews analog circuitries for processing of data to improve energy efficiency in addition to low power networking protocols and security solutions.