Negin Golshani

Monolithic 3D integration of SRAM and image sensor using two layers of single grain silicon

In this paper we report the monolithic integration of two single grain silicon layers for SRAM and image sensor applications. A 12 × 28 silicon lateral photodiode array with a 25_μm pixel size prepared on top of a three transistor readout circuit with individual outputs for every pixel is demonstrated. 6T SRAM cells with two layers of stacked transistors were prepared to compare the performance and area of each cell in different configurations.

Robust UV/VUV/EUV PureB Photodiode Detector Technology With High CMOS Compatibility

This paper gives an assessment of old and new data relevant to the optical and electrical performance of PureB photodiodes for application in the wavelength range 2 nm to 400 nm. The PureB layer, fabricated by depositing pure boron on Si, forms the anode region of devices that function as p+n junction diodes. The results show that the high sensitivity and high stability of the PureB diodes is related to the integrity of the interface with the Si. When measures are taken to retain a complete PureB coverage, thermal processing steps with minute long exposure to temperatures up to 900 °C do not compromise the robustness and a lower-than-ideal but still high responsivity is maintained. Besides the thermal processing considerations, other aspects that impact the integration of PureB in CMOS are reviewed.

VUV/Low-Energy Electron Si Photodiodes With Postmetal 400

Pure boron (PureB) chemical-vapor deposition performed at 400°C is applied as a postmetalization process module to fabricate near-ideal p+n photodiodes with nm-thin PureB-only beam-entrance windows. The photodiodes have near-theoretical sensitivity and high stability for optical characterization performed with either UV light down to a wavelength of 270 nm or low-energy electrons down to 200 eV.

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In this paper, we report monolithic integration of two single-grain silicon layers for static random access memory (SRAM) and image sensor applications. A 12 × 28 silicon lateral photodiode array with a 25-μm pixel size prepared on top of a three-transistor readout circuit with individual outputs for every pixel is demonstrated. 6T SRAM cells with two layers of stacked transistors were prepared to compare the performance and area of each cell in different configurations.

PureB Deposition

Integrated resistors are fabricated by using pure boron (PureB) depositions to create a p-type conductive layer on n-type silicon. Sheet resistance values in the 100 kΩ/□ range are reliably and reproducibly realized. The resistors made in this material are linear and display low temperature coefficients of a few hundred ppm/°C and good tolerances.

Monolithic 3-D Integration of SRAM and Image Sensor Using Two Layers of Single-Grain Silicon

An arsenic doping technique for depositing up to 40-μm-thick high-resistivity layers is presented for fabricating diodes with low RC constants that can be integrated in closely-packed configurations. The doping of the as-grown epi-layers is controlled down to 5 × 1011 cm−3, a value that is solely limited by the cleanness of the epitaxial reactor chamber. To ensure such a low doping concentration, first an As-doped Si seed layer is grown with a concentration of 1016 to 1017 cm−3, after which the dopant gas arsine is turned off and a thick lightly-doped epi-layer is deposited. The final doping in the thick epi-layer relies on the segregation and incorporation of As from the seed layer, and it also depends on the final thickness of the layer, and the exact growth cycles. The obtained epi-layers exhibit a low density of stacking faults, an over-the-wafer doping uniformity of 3.6%, and a lifetime of generated carriers of more than 2.5 ms. Furthermore, the implementation of a segmented photodiode electron detector is demonstrated, featuring a 30 pF capacitance and a 90 Ω series resistance for a 7.6 mm2 anode area.

High-ohmic resistors using nanometer-thin pure-boron chemical-vapour-deposited layers

A review is given of present and potential applications of pure dopant deposition of boron and gallium integrated as the p+-region in p+n ultrashallow junctions. Pure B (PureB) layers have been applied in several large area Si diode applications where nm-shallow junctions are required: high-linearity, high-quality varactor diodes for RF adaptive circuits and photodiode detectors for low-penetration-depth beams such as extreme/ vacuum/deep-ultraviolet (EUV, VUV, DUV) light and low-energy electrons. The integration of these types of detectors in CMOS is discussed along with some points that may make the pure dopant depositions attractive for source/drain fabrication in advanced pMOS transistors. Pure Ga capped with pure B (PureGaB) layers have been demonstrated as the p+-region in p+n Ge-on-Si diodes that are sensitive to infrared wavelengths (> 1 μm) both in avalanche and Geiger mode.

Arsenic-doped high-resistivity-silicon epitaxial layers for integrating low-capacitance diodes

In this paper we will report successfully fabricated six transistor static random access memory (6T SRAM) cells using single-grain thin film transistors (TFTs). SRAM cells have been designed by analytical calculations and verified by DC and transient simulations. TFTs are fabricated by µ-Czochralski process that consists of making grain filter and Excimer laser crystallization at temperatures below 550 °C. The gate length of transistors are 2 µm. Fabricated SRAM cells based on single grain TFTs, show good read and write static noise margin (SNM and WNM) equal to 0.55 and 0.75 V at 3.3 V power supply, respectively. Finally, excellent read and write access times equal to 13 and 8 ns in 87 MHz worldline frequency were obtained.