J. Derakhshandeh

Monolithic 3D integration of SRAM and image sensor using two layers of single grain silicon

In this paper we report the monolithic integration of two single grain silicon layers for SRAM and image sensor applications. A 12 × 28 silicon lateral photodiode array with a 25_μm pixel size prepared on top of a three transistor readout circuit with individual outputs for every pixel is demonstrated. 6T SRAM cells with two layers of stacked transistors were prepared to compare the performance and area of each cell in different configurations.

VUV/Low-Energy Electron Si Photodiodes With Postmetal 400

Pure boron (PureB) chemical-vapor deposition performed at 400°C is applied as a postmetalization process module to fabricate near-ideal p+n photodiodes with nm-thin PureB-only beam-entrance windows. The photodiodes have near-theoretical sensitivity and high stability for optical characterization performed with either UV light down to a wavelength of 270 nm or low-energy electrons down to 200 eV.

^{\circ}{\rm C}

A silicon photodiode detector is presented for use in scanning electron microscopy (SEM). Enhanced imaging capabilities are achieved for sub-keV electron energy values by employing a pure boron (PureB) layer photodiode technology to deposit nanometer-thin photosensitive anodes. As a result, imaging using backscattered electrons is demonstrated for 50-eV electron landing energy values. The detector is built up of several closely packed photodiodes, and to obtain high scanning speed, each photodiode is engineered with low series resistance and low capacitance values. The low capacitance (<; 3 pF/mm2) is facilitated by thick, almost intrinsically-doped epitaxial layers grown to achieve the necessarily wide depletion regions. For the low series resistance, diode metallization has been patterned into a conductive grid directly on top of the nanometer-thin PureB-layer front-entrance window. Finally, a through-wafer aperture in the middle of the detector is micromachined for flexible positioning in the SEM system.

PureB Deposition

For the application of carbon nanotubes (CNT) as interconnects in integrated circuits low temperature vertically aligned growth with a high tube density is required. We found that etching and cleaning steps used in semiconductor technology can damage the catalyst or support layer, preventing low temperature aligned CNT growth. We propose to use a lift-off process and sacrificial layer to prevent damage. Using this method we created low temperature electrical measurement structures for CNT bundles. The bundles grown at 500 °C display a low resistivity and good Ohmic contact. Finally, we demonstrate that CNT can be covered by PECVD silicon oxide and nitride without inducing damage, which is of interest for low temperature bottom-up integration.

High-Efficiency Silicon Photodiode Detector for Sub-keV Electron Microscopy

The effect of external mechanical stress on the crystallization of amorphous silicon deposited on thin, flexible glass substrates has been studied. A thin, 5–10 A, layer of nickel deposited on the surface of the amorphous silicon layer acted as the seed of crystallization and the crystallization was observed to initiate at the top surface and proceed down towards the glass substrate. Application of a tensile stress during the annealing stage led to a uniform, partial crystallization of the amorphous silicon for annealing temperatures as low as 310 °C. In contrast, the application of compressive stress led to buckling of the silicon films during annealing under mechanical stress and crystallization was nonuniform over the surface of the sample. The crystalline quality of the films was investigated using scanning electron microscopy, x-ray diffraction, and transmission electron microscopy analyses. In addition, lateral polycrystalline growth of the silicon was observed for the case in which the nickel seed ...

Integrating low temperature aligned carbon nanotubes as vertical interconnects in Si technology

In this paper, we report monolithic integration of two single-grain silicon layers for static random access memory (SRAM) and image sensor applications. A 12 × 28 silicon lateral photodiode array with a 25-μm pixel size prepared on top of a three-transistor readout circuit with individual outputs for every pixel is demonstrated. 6T SRAM cells with two layers of stacked transistors were prepared to compare the performance and area of each cell in different configurations.

Stress-assisted nickel-induced crystallization of silicon on glass

Vertical stacking of transistors is a promising technology which can realize compact and high-speed integrated circuits (ICs) with a short interconnect delay and increased functionality. Two layers of low-temperature fabricated single-grain thin-film transistors (SG TFTs) have been monolithically integrated. Using a finite element method (FEM) simulation, the damage to the bottom layer devices during laser crystallization of the top layer silicon layer has been investigated. N-channel metal–oxide–semiconductor (n-MOS) mobilities are 565 and 393 cm2 V-1 s-1 and p-channel MOS (p-MOS) mobilities are 159 and 141 cm2 V-1 s-1, for the top and bottom layers respectively. A three-dimensional (3D) complementary MOS (CMOS) inverter has also been fabricated, with one transistor on the bottom layer and the other on the top layer.

Monolithic 3-D Integration of SRAM and Image Sensor Using Two Layers of Single-Grain Silicon

An arsenic doping technique for depositing up to 40-μm-thick high-resistivity layers is presented for fabricating diodes with low RC constants that can be integrated in closely-packed configurations. The doping of the as-grown epi-layers is controlled down to 5 × 1011 cm−3, a value that is solely limited by the cleanness of the epitaxial reactor chamber. To ensure such a low doping concentration, first an As-doped Si seed layer is grown with a concentration of 1016 to 1017 cm−3, after which the dopant gas arsine is turned off and a thick lightly-doped epi-layer is deposited. The final doping in the thick epi-layer relies on the segregation and incorporation of As from the seed layer, and it also depends on the final thickness of the layer, and the exact growth cycles. The obtained epi-layers exhibit a low density of stacking faults, an over-the-wafer doping uniformity of 3.6%, and a lifetime of generated carriers of more than 2.5 ms. Furthermore, the implementation of a segmented photodiode electron detector is demonstrated, featuring a 30 pF capacitance and a 90 Ω series resistance for a 7.6 mm2 anode area.

Stacking of Single-Grain Thin-Film Transistors

The effects of plasma-enhanced hydrogenation on the crystallization of pure, electron-beam evaporated amorphous silicon (a-Si) at temperatures as low as 300°C were investigated. Successive steps of hydrogenation in the plasma-enhanced chemical vapor deposition chamber, and in situ annealing in a N2 ambient environment were applied to the a-Si samples over a range of low temperatures and plasma powers. At specific plasma-power densities, nanocrystalline silicon layers with an average grain size of less than 10nm were formed where their size, distribution, and porosity could be varied by altering the plasma power and hydrogenation temperature. The surface morphology and the nanocrystalline quality of the samples were characterized using scanning electron microscopy, dark-field transmission electron microscopy, and electron diffraction. In addition, by plasma-enhanced oxidation at a temperature of 250°C, a thin layer of oxide was grown and its physical, structural, and electrical characteristics were investi...

Arsenic-doped high-resistivity-silicon epitaxial layers for integrating low-capacitance diodes

We have designed and fabricated lateral photodiodes with analog and digital outputs using µ-Czochralski process. The advantage of µ-Czochralski process is crystallization of active silicon layer at low temperature using Excimer laser. In this process, predefined locations on oxide with 1µm squares, called grain filters, are formed to determine the locations of single grain silicon. Then these holes are covered by 870nm PECVD TEOS oxide at 350°C to reduce the size of holes to approximately 0.1µm. After deposition of 250nm LPCVD amorphous silicon at 550°C, Excimer laser is irradiated on silicon at 400°C with 1500mJ/cm2 laser energy. This laser energy can give uniform square grains before ablation. It melts the silicon layer and then crystallization starts from bottom of grain filter where we have solid and un-melted silicon. This technique is suitable for stacking silicon layers to realize monolithic 3DIC. Fabricated TFTs inside single grains are comparable with SOI devices in term of high mobility and high frequency behavior characteristics. [1] The achieved motilities are 500cm2/VS for nMOS and 300cm2/VS for pMOS transistors. Figure 1 shows the schematics of this process and also SEM image of crystallized silicon. The size of grains is more sensitive to laser energy and in average they are in 6µm squares.