C.I.M. Beenakker

Monolithic 3D integration of SRAM and image sensor using two layers of single grain silicon

In this paper we report the monolithic integration of two single grain silicon layers for SRAM and image sensor applications. A 12 × 28 silicon lateral photodiode array with a 25_μm pixel size prepared on top of a three transistor readout circuit with individual outputs for every pixel is demonstrated. 6T SRAM cells with two layers of stacked transistors were prepared to compare the performance and area of each cell in different configurations.

Advanced excimer laser crystallization techniques of Si thin film for location control of large grain on glass

This paper reviews advanced excimer-laser crystallization techniques and its application to crystal-Si thin film transistors (TFTs). Combined microstructure and time- resolved optical reflectivity investigations during conventional excimer-laser crystallization showed that explosive crystallization occurs during excimer-laser irradiation. Two methods enabling location-control of large silicon islands will be reviewed. One of the methods uses local thermal relief by modifying locally the heat extraction rate towards the substrate. A small unmolten region remains at the center of high heat extraction part which then acts as a seed for radially grown Si grain with a diameter of 6 micrometers . One of the other methods use geometric selection through a vertical narrow constriction. In this method, upon laser irradiation, a small unmolten Si region remains at the bottom of narrow holes etched in the underlying isolation layer. During vertical regrowth, a single grain is filtered out which subsequently seeds the lateral growth of large grains. We will also discuss the performance of crystal-silicon TFTs that are formed in the location-controlled Si grains. The field-effect mobility for electrons is 450 cm2Vs, which is very close to that of TFTs made with silicon-on-insulator wafers.

Single-grain Si TFTs with ECR-PECVD gate SiO/sub 2/

High-performance Si thin-film transistors (TFTs) are fabricated inside a single, location-controlled grain with gate SiO/sub 2/ deposited by electron cyclotron resonance plasma enhanced chemical vapor deposition (ECR-PECVD). The position of the large grains is controlled by /spl mu/-Czochralski (grain-filter) process with excimer-laser crystallization. Owing to the low interface trap density of ECR-PECVD SiO/sub 2/ the single-grain Si TFTs showed a smaller subthreshold swing of 0.45 V/decade, in addition to a higher field-effect mobility for electrons of 460 cm/sup 2//Vs than that with low-pressure chemical-vapor deposited (LPCVD) SiO/sub 2/.

Integrating low temperature aligned carbon nanotubes as vertical interconnects in Si technology

For the application of carbon nanotubes (CNT) as interconnects in integrated circuits low temperature vertically aligned growth with a high tube density is required. We found that etching and cleaning steps used in semiconductor technology can damage the catalyst or support layer, preventing low temperature aligned CNT growth. We propose to use a lift-off process and sacrificial layer to prevent damage. Using this method we created low temperature electrical measurement structures for CNT bundles. The bundles grown at 500 °C display a low resistivity and good Ohmic contact. Finally, we demonstrate that CNT can be covered by PECVD silicon oxide and nitride without inducing damage, which is of interest for low temperature bottom-up integration.

Monolithic 3-D Integration of SRAM and Image Sensor Using Two Layers of Single-Grain Silicon

In this paper, we report monolithic integration of two single-grain silicon layers for static random access memory (SRAM) and image sensor applications. A 12 × 28 silicon lateral photodiode array with a 25-μm pixel size prepared on top of a three-transistor readout circuit with individual outputs for every pixel is demonstrated. 6T SRAM cells with two layers of stacked transistors were prepared to compare the performance and area of each cell in different configurations.

An anisotropic U-shaped SF6-based plasma silicon trench etching investigation

Abstract Anisotropic etching of silicon has been studied in SF6/O2/He plasma using a multivariable experimental design. It has been found that the main monitored responses of the etching process such as silicon etch rate, selectivity of silicon over oxide, etch uniformity and etch anisotropy were influenced by a combination of independent variables. The most important variables were RF power, chamber pressure, total gas flow and oxygen content (i.e., percentage of the O2 flow in the total gas flow). The physical and chemical explanations have been based upon the etching models obtained with the Response Surface Methodology (RSM). The models were subsequently used to optimise the etching process for trench isolation applications. The optimal values of process parameters for U-shaped 4 μm trench etching with anisotropy of 0.97 have been found. Applications of the trenches obtained have been tested at low/high doped multilayer structures.

High performance single grain si tfts inside a location-controlled grain by /spl mu/-czochralski process with capping layer

To enlarge the grain size of 2D location-controlled Si grain by mu-Czochralski process, capping layer (C/L) of SiO₂ in excimer-laser crystallization of amorphous Si thin film has been employed. With a 50 nm thick SiO₂ C/L on a 100 nm thick amorphous Si film, the diameter of the location-controlled grain was successfully increased up to 7.5 mum. Single-grain (SG) Si TFTs were fabricated inside a location-controlled grain with the SiO₂ C/L as a part of the gate oxide. Field effect mobility (mu_FE) for electrons and holes of 510 cm²/Vs and of 210 cm²/Vs were obtained respectively

Plasma decapsulation of plastic IC packages with copper wire bonds for failure analysis

Decapsulation of plastic integrated circuit (IC) packages with copper wire bonding is achieved by using an atmospheric pressure microwave induced plasma. A thermal model is built to estimate the bulk IC package temperature under different plasma etching conditions. Temperature measurements of the plasma effluent and IC package are made to validate the model. Due to the low heat transfer rate from gas to solid, the plasma effluent of 700°C raises the bulk temperature of an IC package to 150°C only. This brings a great advantage in processing because a high temperature on a focused area where the plasma etching takes place results in a high etching rate, while a low IC package bulk temperature ensures minimum thermally induced damage to the internal components. Recipes for three etching steps are developed. An IC package with 38 um copper wire bonds and a 2 mm ∗ 3.5 mm die is decapsulated in 20 minutes. Copper bond wires, aluminum bond pads, and structures on the die are undamaged after decapsulation.

Property of single-crystalline Si TFTs fabricated with μ-Czochralski (grain filter) process

Formation of TFTs inside location-controlled large Si grains with a low temperature process is an attractive approach for realizing system-circuit integration with displays on a large glass substrate. Local structural variations of the substrate using photolithography allows an accurate location-control of the large Si grains in excimer-laser crystallization. Single-crystalline Si (c-Si) TFTs was formed inside a location-controlled large (6 μm) grain by μ-Czochraski process of a-Si film. The c-Si TFTs showed field effect mobility of 450 cm2/Vs on average. Crystallization characteristics, spread of the TFT characteristics and effects of process parameters will be reviewed and discussed.

Phase-field modelling of excimer laser lateral crystallization of silicon thin films

A 2D phase-field model was applied to simulate the phase-transition kinetics and the thermal field distribution during the lateral crystallization of a-Si induced by single pulse excimer laser. The higher tilt of solid/liquid interface increases the supercooling temperature in the melt due to the fast latent heat extraction at the solid/liquid interface. The lateral growth velocity is in average four times faster than the vertical one. When the lateral growth velocity exceeds the critical value of 19 m/s, amorphization of Si can be initiated because of unstable growth front. Therefore, thickness of Si film and the thermal properties of underlying layer play a crucial role not only in ultra-large grain fabrication but also in defect-free crystal growth.