Nenad Pavlovic

A 5.3GHz digital-to-time-converter-based fractional-N all-digital PLL

Advanced deep-submicron CMOS processes are well-suited for a digital implementation of phase-locked loop-(PLL) based frequency synthesizers. Recently, several RF all-digital phase-locked loops (ADPLL) have been reported [2,4,5]. While ADPLLs come close to achieving the phase-noise performance of analog PLLs, the in-band spur level requirement is still challenging. In this paper we present a new digital-to-time-converter-(DTC) based ADPLL architecture where the time resolution can be easily scaled.

A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18/spl mu/m CMOS technology

A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at 2.5GHz. The jitter and power dissipation are lower than that of previous CMOS implementations.

A 1.2V, 17dBm digital polar CMOS PA with transformer-based power interpolating

Targeting for WLAN applications, this paper presents a digital polar power amplifier in a 65 nm digital CMOS process, with 17 dBm maximum RMS output power at 1.2 V supply voltage. To reduce the out-of-band alias caused in the direct digital-to-RF power conversion, a transformer-based power interpolating technique is implemented. This also improves the average efficiency by adaptively configuring the interpolation stages. The measured power added efficiency remains between 8.9% and 12.7% over power range from 12 dBm to 17 dBm. The achieved power level allows for eliminating the commonly used external PA stage.

A wideband single-PLL RF receiver for simultaneous multi-band and multi-channel digital car Radio reception

This paper describes a single-PLL, fixed-oscillator, wide-band multi-tuner HD Radio & DAB/T-DMB receiver for concurrent multi-band & multi-channel car radio reception, fully integrated in a 65nm CMOS SoC. Besides saving area and power for the LO and clock generation, the presented architecture also prevents oscillator pulling and spurs. Harmonic rejection mixers have been used to suppress down-conversion with LO harmonics up to 60dB, which reduces the required amount of RF filtering. The DAB measurement results show best-in-class blocker performance (FoS up to 70dBc) in combination with state-of-the-art sensitivity down to -102dBm.

A 6.5 GHz Arbitrary Digital Waveform Generator

An Arbitrary Digital Waveform Generator is presented, capable of producing any 32-bit or shorter output sequence on the input clock half-period timing grid. An extension module allows additional outputs with time-shifted versions of the first output. The modular concept is demonstrated driving a passive 25% duty-cycle mixer. The packaged prototype, fabricated in 65-nm baseline CMOS, achieves calibration-free operation up to an unprecedented input clock speed of 6.5 GHz, consumes 12 mA with a single differential output and 18 mA as multiphase mixer driver, both from 1.2 V supplies. The combined chip area, including all required logic, is 0.023 mm2.