Nestoras Tzartzanis

Low-power digital systems based on adiabatic-switching principles

Adiabatic switching is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. When adiabatic switching is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. We describe the fundamental adiabatic amplifier circuit and analyze its performance. The dissipation of the adiabatic amplifier is compared to that of conventional switching circuits, both for the case of a fixed voltage swing and the case when the voltage swing can be scaled to reduce power dissipation. We show how combinational and sequential adiabatic-switching logic circuits may be constructed and describe the timing restrictions required for adiabatic operation. Small chip-building experiments have been performed to validate the techniques and to analyse the associated circuit overhead. >

A low-power microprocessor based on resonant energy

We describe AC-1, a CMOS microprocessor that derives most of its operating power from the clock signals rather than from dc supplies. Clock-powered circuit elements are selectively used to drive high-fan-out nodes. An inductor-based, all-resonant clock-power generator allows us to recover 85% of the clock-drive energy. The measured top frequency for the microprocessor was 58.8 MHz at 26.2 mW. The resulting overall decrease in dissipation ranges from four to five times at clock frequencies from 35 to 54 MHz. We also compare the performance of the processor to a reimplementation in static logic.

AC-1: a clock-powered microprocessor

We describe the design of AC-1, a low-power 16-bit microprocessor which utilizes clock-powered logic to reduce dissipation in its power-intensive sections. We present power measurements for a 0.5-/spl mu/m n-well CMOS implementation. A resonant clock driver recovers and reuses energy that would otherwise be dissipated as heat, yielding measured overall power reduction factors of four to five.

Energy recovery for the design of high-speed, low-power static RAMs

We present a low-power SRAM design based on the theory of energy recovery that reduces the dissipation associated with write operations while operating at high speed. The energy-recovery SRAM was evaluated through SPICE simulations and compared with a standard design. Simulation results of a 256 × 256 memory configuration indicate that, for successive write operations, energy saving for the different SRAM functions vary from 59% to 76% at 200 MHz operating frequency compared to the conventional design.

The design and implementation of a low-power clock-powered microprocessor

We describe the design and implementation of a 16-bit clock-powered microprocessor that dissipates only 2.9 mW at 15.8 MHz based on laboratory measurements. Clock-powered logic (CPL) has been developed as a new approach for designing and building low-power VLSI systems that exploit the benefits of supply-voltage-scaled static CMOS and energy-recovery CMOS techniques. In CPL, the clock signals are a source of ac power for the other large on-chip capacitive loads. Clock amplitude and waveform shape combine to reduce power. By exploiting energy recovery and an energy-conserving clock driver, it is possible to build ultra-low-power CMOS processors with this approach. We compare the CPL approach with a conventional, fully dissipative approach for a processor with a similar ISA and VLSI architecture which was designed using the same set of VLSI CAD tools. The simulation results indicate that the CPL microprocessor would dissipate 40% less power than the conventional design.

Design and analysis of a low-power energy-recovery adder

In this paper, an 8-bit energy-recovery adder design is evaluated through SPICE simulation for energy dissipation and delay time, and is compared against a supply-voltage-scaled adder. The experimental results indicate that the energy-recovery adder outperforms the supply-scaled version for a wide range of frequencies.

Energy recovery for low-power CMOS

Energy recovery, as a means to trade off power dissipation for performance in CMOS logic circuits, is analyzed and investigated. A mathematical model is presented to estimate the efficiency for two energy-recovery approaches under varying conditions of voltage swing, transition time, and MOS device parameters. This model can be directly compared to the well-known model for supply-voltage scaling, which is the prevalent method for trading power dissipation for performance. The two models are evaluated against SPICE simulations. Excluding body effects, which would not be present in CMOS process technologies such as Silicon-On-Insulator (SOI), the simulations and the equations agree to within 10%. The simulations also indicate that energy recovery, when implemented with circuit techniques such as bootstrapping, can significantly outperform the supply-voltage-scaled approach across a wide range of operating frequencies. To further investigate this result, two eight-bit adder designs, one based on supply-voltage scaling and the other on energy recovery, are simulated and compared.

Clock-powered CMOS VLSI graphics processor for embedded display controller application

This paper describes a 16 b clock-powered microprocessor that dissipates only 2.9 mW at 15.8 MHz from laboratory measurements. Clock-powered logic (CPL) has been developed as a new approach for designing and building low-power VLSI systems. In CPL, the clock signals serve as a source of ac power for the large on-chip capacitive loads. By exploiting adiabatic charging and an energy conserving clock driver, it is possible to build ultra-low-power CMOS processors with this approach. Previously, a CPL processor was demonstrated in a 0.5 /spl mu/m n-well CMOS process. Laboratory measurements confirmed that it was possible and practical to recover and reuse large amounts (upwards of 80%) of the on-chip capacitive energy for a 16 b pipelined general-purpose CMOS processor. The measurements and simulation data analysis also pointed out some of the shortcomings of the original design approach which limited the speed, voltage scalability, and robustness of the processor.

Clock-powered CMOS: a hybrid adiabatic logic style for energy-efficient computing

Clock-powered logic is a new CMOS logic style which combines adiabatic switching and energy recovery-techniques with conventional CMOS logic styles for the design of low-power computing microsystems. In clock-powered logic high-capacitance nodes are adiabatically switched and powered from AC sources typically the clock lines. Low-capacitance nodes are conventionally switched and powered front a DC supply source. The clocked buffer, a CMOS structure based on bootstrapping, drives the high-capacitance nodes from the clock lines. An analytical model that closely estimates the on-resistance of the bootstrapped nFET is derived. The model is evaluated through H-SPICE simulations. Depending on the CMOS logic style used for the DC-powered blocks, pulse-to-level converters may be required to interface the clocked buffer outputs with the logic blocks. These converters inherently act as low-to-high voltage converters. Therefore, low-power operation can be achieved with clock-powered logic by both increasing the switching time and reducing the voltage swing of clock-powered nodes. This feature of clock-powered logic is evaluated through H-SPICE simulations in which the clocked buffer is compared with conventional supply-scaled CMOS drivers. The clocked buffer combined with adiabatic switching demonstrates superior energy vs. delay scalability than its supply-scaled counterparts.

Retractile clock-powered logic

Retractile clock-powered logic is presented as a low-overhead energy-recovery logic style. It uses energy-efficient clock-steering circuits, pass-transistor logic, and a four-phase clocking scheme to recover energy from all circuit nodes but the latches. A 16-bit retractile clock-powered adder is described and evaluated through HSPICE simulations. The simulation results indicate that this approach can offer superior energy vs. delay performance but the benefit depends strongly on the switching activity of the clock-powered nodes.