William C. Athas

Low-power digital systems based on adiabatic-switching principles

Adiabatic switching is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. When adiabatic switching is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. We describe the fundamental adiabatic amplifier circuit and analyze its performance. The dissipation of the adiabatic amplifier is compared to that of conventional switching circuits, both for the case of a fixed voltage swing and the case when the voltage swing can be scaled to reduce power dissipation. We show how combinational and sequential adiabatic-switching logic circuits may be constructed and describe the timing restrictions required for adiabatic operation. Small chip-building experiments have been performed to validate the techniques and to analyse the associated circuit overhead. >

Adiabatic Switching, Low Energy Computing, And The Physics Of Storing And Erasing Information

A new CMOS logic family allows the design of digital computing circuits that are more energy efJicient than conventional CMOS circuits, and that become increasingly energy efficient the slower they are operated. 7ke properties of the new logic family support Landauer’s thermodynamically motivated conjecture that the only necessarily dissipative opertion in compution is the erasure of information. Also, they suggest that there is an analogous result in switching theory, which bounds below the energy dissipation in circuits containing feedback. In this paper, we sketch the principles of the new logic family, and discuss some intuitive insights which might be useful in constructing a rigorous proof of a switching-theoretic analog of Landuaer’s principle.

An energy-efficient CMOS line driver using adiabatic switching

Describes a custom CMOS line driver chip and a resonant power supply that can switch eight 100 pF loads at 1 MHz six times more efficiently than a conventional (CV/sup 2/) CMOS solution. The authors describe the adiabatic charging principle used, which allows a digital circuit designer to directly trade off switching time for increased energy efficiency. Emphasis is placed on evaluating the dissipation overhead for the whole system including the power supply. Measurements confirm the predicted dissipation decrease.<<ETX>>

A low-power microprocessor based on resonant energy

We describe AC-1, a CMOS microprocessor that derives most of its operating power from the clock signals rather than from dc supplies. Clock-powered circuit elements are selectively used to drive high-fan-out nodes. An inductor-based, all-resonant clock-power generator allows us to recover 85% of the clock-drive energy. The measured top frequency for the microprocessor was 58.8 MHz at 26.2 mW. The resulting overall decrease in dissipation ranges from four to five times at clock frequencies from 35 to 54 MHz. We also compare the performance of the processor to a reimplementation in static logic.

A resonant signal driver for two-phase, almost-non-overlapping clocks

We describe a driver circuit for reducing the power dissipated when driving heavily loaded signals such as the clock lines of a VLSI chip. The design exhibits good power efficiency across a wide range of frequencies. We have tested the driver with a prototype shift-register chip which had a clock line load in the hundreds of picofarads. The worst-case overall dissipation was 35% of fCV/sup 2/ at 13 MHz and 5 V.

Reversible logic issues in adiabatic CMOS

Power dissipation in CMOS circuits has become increasingly important for the design of portable, embedded and high-performance computing systems. Our VLSI research group has investigated a novel form of energy-conserving logic suitable for CMOS. Through small chip-building experiments, we have demonstrated the low-power operation of simple logic functions. These chips have used logical reversibility on a small, sometimes trivial, scale to achieve their low-power operation. In moving towards more complex functions, the role of reversibility will increase. This paper addresses two problem areas that we have found to be crucial to successfully realizing low-power operation of CMOS chips using reversible logic techniques. The first area is the energy-efficient design of the combined power supply and clock generator. The second is the logical overhead needed to support reversible logic functions. The first problem area, though formidable, seems amenable to systematic approaches. Significant inroads have been made towards finding practical, efficient solutions. The second, however, appears to be by far the more difficult hurdle to overcome irreversible logic is to become an attractive approach for reducing power dissipation in CMOS.<<ETX>>

AC-1: a clock-powered microprocessor

We describe the design of AC-1, a low-power 16-bit microprocessor which utilizes clock-powered logic to reduce dissipation in its power-intensive sections. We present power measurements for a 0.5-/spl mu/m n-well CMOS implementation. A resonant clock driver recovers and reuses energy that would otherwise be dissipated as heat, yielding measured overall power reduction factors of four to five.

Energy recovery for the design of high-speed, low-power static RAMs

We present a low-power SRAM design based on the theory of energy recovery that reduces the dissipation associated with write operations while operating at high speed. The energy-recovery SRAM was evaluated through SPICE simulations and compared with a standard design. Simulation results of a 256 × 256 memory configuration indicate that, for successive write operations, energy saving for the different SRAM functions vary from 59% to 76% at 200 MHz operating frequency compared to the conventional design.

Design and analysis of a low-power energy-recovery adder

In this paper, an 8-bit energy-recovery adder design is evaluated through SPICE simulation for energy dissipation and delay time, and is compared against a supply-voltage-scaled adder. The experimental results indicate that the energy-recovery adder outperforms the supply-scaled version for a wide range of frequencies.

Energy recovery for low-power CMOS

Energy recovery, as a means to trade off power dissipation for performance in CMOS logic circuits, is analyzed and investigated. A mathematical model is presented to estimate the efficiency for two energy-recovery approaches under varying conditions of voltage swing, transition time, and MOS device parameters. This model can be directly compared to the well-known model for supply-voltage scaling, which is the prevalent method for trading power dissipation for performance. The two models are evaluated against SPICE simulations. Excluding body effects, which would not be present in CMOS process technologies such as Silicon-On-Insulator (SOI), the simulations and the equations agree to within 10%. The simulations also indicate that energy recovery, when implemented with circuit techniques such as bootstrapping, can significantly outperform the supply-voltage-scaled approach across a wide range of operating frequencies. To further investigate this result, two eight-bit adder designs, one based on supply-voltage scaling and the other on energy recovery, are simulated and compared.