Nghia Tang

DVFS Pruning for Wireless NoC Architectures

The millimeter wave small world network on a chip is an emerging paradigm to design low power and high-bandwidth massive multicore chips. By reducing the hop count between largely separated communicating cores, wireless shortcuts in mSWNoC have been shown to carry a significant amount of the overall traffic within the network. The amount of traffic detoured in this way is substantial and the low power wireless links enable energy savings [1]. The overall energy dissipation and thermal profile of the mSWNoC can be improved even further if the characteristics of the wireline links and associated switches are optimized according to the traffic patterns. Dynamic voltage and frequency scaling (DVFS) is a popularmethodology to optimize the power usage/heat dissipation of electronic systems without significantly compromising overall system performance.We have already demonstrated that DVFS enables improvement of power and thermal profiles of mSWNoC-enabled multicore chips.

A Self-Sustainable Power Management System for Reliable Power Scaling Up of Sediment Microbial Fuel Cells

Sediment microbial fuel cells (SMFCs) are considered a promising renewable power source for remote monitoring applications. However, existing SMFCs can only produce several milliwatts of power, and the output power is not scaled linearly with the size of SMFCs. An effective alternative method to increase the output power is to independently operate multiple SMFCs, each of which has an optimal size for maximum power density. Independently operated SMFCs have electrically isolated electrodes (anodes/cathodes), which complicates the design of a suitable power management system (PMS). This paper describes the challenges in designing a PMS that can harvest energy from multiple independently operated (mio) SMFCs and accordingly proposes a design solution. From experimental results, the proposed PMS demonstrates reliable output power scaling up of mio-SMFC. The proposed PMS is self-sustainable because it is powered entirely from harvested energy without requiring additional external power sources.

A Sub-1-V Bulk-Driven Opamp With an Effective Transconductance-Stabilizing Technique

The effective transconductance (G_m) of a bulkdriven operational amplifier (opamp) can significantly vary with the input common-mode voltage. This variation of G_m complicates frequency compensation and creates harmonic distortion. Thus, this brief presents a G_m-stabilizing technique to reduce the variation of G_m across the input common-mode range (ICMR). The idea is to use a variable positive feedback structure to adaptively control G_m to the input common-mode voltage. A low-voltage bulk-driven opamp with the proposed G_m-stabilizing technique has been implemented in a 0.18-μm n-well CMOS process. The opamp consumes 261 μW from a 900-mV supply voltage. The variation of G_m is reduced from 132% to 25% across the rail-to-rail ICMR. The measured dc gain is 76.8 dB and the unity-gain bandwidth is 7.11 MHz when the opamp is loaded with 17 pFII1 MΩ.

PWM-skipping technique for overshoot and undershoot mitigation

ABSTRACT Overshoot and undershoot resulted from line/load/reference change can degrade the power efficiency of a voltage regulator. A pulse width modulation (PWM) skipping technique is thus proposed to reduce such voltage fluctuation. A four-phase interleaved buck converter is experimented to verify the merits of the proposed technique. In steady-state operation, all four phases of the buck converter are driven by a PWM controller to regulate the output voltage. During transient response, the PWM-skipping technique bypasses the PWM controller to drive some phases of the buck converter into charging or discharging state. Simulation results demonstrate that the proposed PWM-skipping technique effectively reduces overshoot and undershoot by more than 25% when the buck converter responds to line/load/reference change.

Fully Integrated Buck Converter with Fourth-Order Low-Pass Filter and Quasi-V 2 Controller

Fully integrated buck converters are typically operated with a second-order LC low-pass filter and a switching frequency beyond 100 MHz. The motivation for such design choices is to reduce the size of passive components in the LC low-pass filter required for small output voltage ripple. However, in a buck converter with on-chip planar spiral inductors, a fourth-order filter can deliver better performance characteristics without area penalty. This paper presents a comparative study of a fourth-order LC low-pass filter versus a second-order LC low-pass filter with on-chip planar spiral inductors and on-chip capacitors. A fully integrated buck converter is then designed with a quasi-V2 controller to demonstrate the benefits of a fourth-order LC low-pass filter. The prototype chip, which is implemented in a 65-nm CMOS process, produces a nominal voltage of 0.7 V from a 1-V supply. The fourth-order LC low-pass filter uses a total inductance of 1.8 nH and a total capacitance of 4 nF. Measurement results demonstrate fast transient response on the order of nanoseconds. A peak efficiency of 76.1% is achieved, and the output voltage ripple is kept below 15 mV over the entire range of load current from 40 to 180 mA.