Ngoc Duy Nguyen

Selective Area Growth of InP in Shallow-Trench-Isolated Structures on Off-Axis Si(001) Substrates

In this paper, we report a comprehensive investigation of InP selective growth in shallow trench isolation (STI) structures on Si(001) substrates 6° off-cut toward (111). Extended defect-free InP layers were obtained in the top region of 100 nm wide trenches. A thin Ge epitaxial layer was used as an intermediate buffer layer between the Si substrate and the InP layer. A Ge buffer was used to reduce the thermal budget for surface clean and to promote double-step formation on the surfaces. Baking the Ge surface in an As ambient improved the InP surface morphology and crystalline quality. InP showed highly selective growth in trenches without nucleation on SiO 2 . However, strong loading effects were observed at all growth pressures, which induced variation in local growth rates. We found trench orientation dependence of facet and stacking fault formation. More stacking faults and nanotwins originated from the STI sidewalls in [110] trenches. High quality InP layers were obtained in the top of the trenches along [110]. The stacking faults generated by the dissociation of threading dislocations are trapped at the bottom of the trenches with an aspect ratio greater than 2.

Thermal admittance spectroscopy of Mg-doped GaN Schottky diodes

Thermal admittance spectroscopy measurements at temperatures ranging from room temperature to 90 K are performed on Schottky structures based on Mg-doped GaN layers grown by metalorganic vapor phase epitaxy on sapphire. The analysis of the experimental data is made by a detailed theoretical study of the steady-state and small-signal electrical characteristics of the structures. Numerical simulations are based on the solution of the basic semiconductor equations for the structure consisting of two Schottky diodes connected back to back by a conduction channel formed by the GaN layer. The description explicitly includes the Mg-related acceptor level, with its temperature- and position-dependent incomplete occupation state, leading to a dynamic exchange with the valence band. It fully reproduces the variations with temperature of the capacitance–frequency and conductance over frequency curves, allowing to give for all temperature ranges the origin of the various contributions to the junction capacitance and of the microscopic mechanisms responsible for the capacitance–frequency cutoff. Series resistance effects are shown to be dominant at temperatures above 230 K, whereas the Mg-related acceptor level governs the electrical behavior below 230 K. The existence of a second acceptor level with an activation energy of several tens of meV is revealed from the analysis of the characteristics at low temperature. An optimized fitting procedure based on the comparison of the electrical characteristics obtained from the numerical simulations to the experimental data allows one to determine the microscopic parameters describing the structure, among which the acceptor activation energies, thermal capture cross sections, concentrations, and the Schottky contact barrier heights are the most important ones. The obtained activation energy of the Mg-acceptor level of 210 meV is by a factor of 2 larger than that obtained from a classical Arrhenius plot, showing that a complete description of Mg-doped GaN junctions requires the correct treatment of the Mg level, acting as a dopant and as deep impurity, as well as the inclusion of series resistance effects.

High- k gate stacks on low bandgap tensile strained Ge and GeSn alloys for field-effect transistors

We present the epitaxial growth of Ge and Ge0.94Sn0.06 layers with 1.4% and 0.4% tensile strain, respectively, by reduced pressure chemical vapor deposition on relaxed GeSn buffers and the formation of high-k/metal gate stacks thereon. Annealing experiments reveal that process temperatures are limited to 350 °C to avoid Sn diffusion. Particular emphasis is placed on the electrical characterization of various high-k dielectrics, as 5 nm Al2O3, 5 nm HfO2, or 1 nmAl2O3/4 nm HfO2, on strained Ge and strained Ge0.94Sn0.06. Experimental capacitance-voltage characteristics are presented and the effect of the small bandgap, like strong response of minority carriers at applied field, are discussed via simulations.

Vapor phase doping with N-type dopant into silicon by atmospheric pressure chemical vapor deposition

Atomic layer doping of phosphorus (P) and arsenic (As) into Si was performed using the vapor phase doping (VPD) technique. For increasing deposition time and precursor gas flow rate, the P and As doses tend to saturate at about 0.8 and 1.0 monolayer of Si, respectively. Therefore, these processes are self-limited in both cases. When a Si cap layer is grown on the P-covered Si(001), high P concentration of 3.7 × 10 20 cm -3 at the heterointerface in the Sicap/P/Si-substrate layer stacks is achieved. Due to As desorption and segregation toward the Si surface during the temperature ramp up and during the Si-cap growth, the As concentration at the heterointerface in the Si-cap/As/Si-substrate layer stacks was lower compared to the P case. These results allowed us to evaluate the feasibility of the VPD process to fabricate precisely controlled doping profiles.

Electrical conduction by interface states in semiconductor heterojunctions

Electrical conduction in semiconductor heterojunctions containing defect states in the interface region is studied. As the classical drift-diffusion mechanism cannot in any case explain electrical conduction in semiconductor heterojunctions, tunnelling involving interface states is often considered as a possible conduction path. A theoretical treatment is made where defect states in the interface region with a continuous energy distribution are included. Electrical conduction through this defect band then allows the transit of electrons from the conduction band of one semiconductor to the valence band of the second component. The analysis is initiated by electrical measurements on n-CdS/p-CdTe heterojunctions obtained by chemical vapour deposition of CdS on (111) oriented CdTe single crystals, for which current-voltage and capacitance-frequency results are shown. The theoretical analysis is based on the numerical resolution of Poissons equation and the continuity equations of electrons, holes and defect states, where a current component corresponding to the defect band conduction is explicitly included. Comparison with the experimental curves shows that this formalism yields an efficient tool to model the conduction process through the interface region. It also allows us to determine critical values of the physical parameters when a particular step in the conduction mechanism becomes dominant.

Si/SiGe Resonant Interband Tunneling Diodes Incorporating

This is the first report of a Si/SiGe resonant interband tunneling diodes (RITDs) on silicon substrates grown by the chemical vapor deposition process. The nominal RITD structure forms two quantum wells created by sharp delta-doping planes which provide for a resonant tunneling condition through the intrinsic spacer. The vapor phase doping technique was used to achieve abrupt degenerate doping profiles at higher substrate temperatures than previous reports using low-temperature molecular beam epitaxy, and postgrowth annealing experiments are suggestive that fewer point defects are incorporated, as a result. The as-grown RITD samples without postgrowth thermal annealing show negative differential resistance with a recorded peak-to-valley current ratio up to 1.85 with a corresponding peak current density of 0.1 kA/cm2 at room temperature.

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An improved fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process is described. An fMAX value of 400GHz is reached by structural as well as intrinsic advancements made to the HBT device.

-Doping Layers Grown by Chemical Vapor Deposition

The effect of the deep acceptor Mg on the electrical characteristics of p-doped GaN Schottky diodes is analyzed. The theoretical study is based on the numerical resolution of the basic semiconductor equations, including the continuity equation for the Mg-related acceptor level. It gives the steady-state and small-signal analysis of p-doped GaN:Mg Schottky diodes, yielding as final result the frequency dependent capacitance and conductance of the structure. It is shown that the low-frequency characteristics are determined by the carrier exchange between the Mg related impurity level and the valence band, whereas above the impurity transition frequency, the hole modulation of the depletion layer edge governs the electrical response. Detailed results are shown on the effect of temperature, applied steady-state voltage and series resistance. The study of two back-to-back connected GaN Schottky diodes reveals the appearance of typical features in the electrical characteristics, depending on the respective Scho...

A 400GHz f MAX fully self-aligned SiGe:C HBT architecture

SSOI substrates were successfully fabricated using He ion implantation and annealing to relax thin (< 500nm) SiGe buffer layers, bonding and layer transfer processes to realize strained-Si layers onto oxide layers. The reduced thickness of the SiGe buffer possess numerous advantages such as reduced process costs for epitaxy and for reclaim of the handle wafer if the layer splitting is initiated in the SiGe/Si interface. The electron mobilities in the fabricated SSOI layers were measured using transistors with different gate lengths. An electron mobility of ~530 cm /Vs was extracted, being much higher than in non-strained SOI substrates. Furthermore, an 80% drive current (IDSAT) improvement has been measured for long channel devices.

Competition between deep impurity and dopant behavior of Mg in GaN Schottky diodes

We have deposited III-V alloys on 200 mm Si miscut wafers with an oxide pattern. The selective epitaxial growth (SEG) of GaAs in large windows defined by SiO2 lines on a thick strained-relaxed Ge buffer layer served as a test vehicle which allowed us to demonstrate the integration of a III-V material deposition process step in a Si manufacturing line using an industrial reactor. High quality GaAs layers with high wafer-scale thickness uniformity were achieved. In a subsequent step, SEG of InP was successfully performed on wafers with a 300 nm shallow trench isolation pattern. The seed layer morphology depended on the treatment of the Ge surface and on the growth temperature. The orientation of the trench with respect to the substrate miscut direction had an impact on the quality of the InP filling. Despite of the challenges, such an approach for the integration of III-V materials on Si substrates allowed us to obtain extended-defect-free epitaxial regions suitable for the fabrication of high-performance devices.