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Dive into the research topics where Roger Loo is active.

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Featured researches published by Roger Loo.


Applied Physics Letters | 2011

Undoped and in-situ B doped GeSn epitaxial growth on Ge by atmospheric pressure-chemical vapor deposition

Benjamin Vincent; Federica Gencarelli; Hugo Bender; Clement Merckling; Bastien Douhard; Dirch Hjorth Petersen; Ole Hansen; Henrik Hartmann Henrichsen; Johan Meersschaut; Wilfried Vandervorst; Marc Heyns; Roger Loo; Matty Caymax

In this letter, we propose an atmospheric pressure-chemical vapor deposition technique to grow metastable GeSn epitaxial layers on Ge. We report the growth of defect free fully strained undoped and in-situ B doped GeSn layers on Ge substrates with Sn contents up to 8%. Those metastable layers stay fully strained after 30 min anneal in N2 at 500 °C; Ge-Sn interdiffusion is seen at 500 °C but not at lower temperature. B is 100% active in the in-situ GeSn:B layers up to a concentration of 1.7 × 1019 cm−3. GeSn:B provides slightly lower Hall hole mobility values than in pure p-type Ge especially for low B concentrations.


Optics Express | 2012

GeSn/Ge heterostructure short-wave infrared photodetectors on silicon

Alban Gassenq; Federica Gencarelli; J. Van Campenhout; Yosuke Shimura; Roger Loo; G Narcy; Benjamin Vincent; Günther Roelkens

A surface-illuminated photoconductive detector based on Ge0.91Sn0.09 quantum wells with Ge barriers grown on a silicon substrate is demonstrated. Photodetection up to 2.2µm is achieved with a responsivity of 0.1 A/W for 5V bias. The spectral absorption characteristics are analyzed as a function of the GeSn/Ge heterostructure parameters. This work demonstrates that GeSn/Ge heterostructures can be used to developed SOI waveguide integrated photodetectors for short-wave infrared applications.


IEEE Photonics Technology Letters | 2013

Germanium-on-Silicon Mid-Infrared Arrayed Waveguide Grating Multiplexers

Aditya Malik; Muhammad Muneeb; Shibnath Pathak; Yosuke Shimura; Joris Van Campenhout; Roger Loo; Günther Roelkens

In this letter, we describe the use of a germanium-on-silicon waveguide platform to realize an arrayed waveguide grating (AWG) operating in the 5 μm wavelength range, which can be used as a wavelength multiplexer for mid-infrared (midIR) light engines or as the core element of a midIR spectrometer. Ge-on-Si waveguide losses in the range 2.5-3.5 dB/cm for TE polarized light and 3-4 dB/cm for TM polarized light in the 5.15-5.4 μm wavelength range are reported. A 200 GHz channel spacing 5-channel AWG with an insertion loss/crosstalk of 2.5/3.1 dB and 20/16 dB for TE and TM polarization, respectively, is demonstrated.


IEEE Journal of Selected Topics in Quantum Electronics | 2014

Silicon-Based Photonic Integration Beyond the Telecommunication Wavelength Range

Günther Roelkens; Utsav Dave; Alban Gassenq; Nannicha Hattasan; Chen Hu; Bart Kuyken; François Leo; Aditya Malik; Muhammad Muneeb; Eva Ryckeboer; Dorian Sanchez; Sarah Uvin; Ruijun Wang; Zeger Hens; Roel Baets; Yosuke Shimura; Federica Gencarelli; Benjamin Vincent; Roger Loo; Joris Van Campenhout; L. Cerutti; Jean-Baptiste Rodriguez; E. Tournié; Xia Chen; Milos Nedeljkovic; Goran Z. Mashanovich; Li Shen; Noel Healy; Anna C. Peacock; Xiaoping Liu

In this paper we discuss silicon-based photonic integrated circuit technology for applications beyond the telecommunication wavelength range. Silicon-on-insulator and germanium-on-silicon passive waveguide circuits are described, as well as the integration of III-V semiconductors, IV-VI colloidal nanoparticles and GeSn alloys on these circuits for increasing the functionality. The strong nonlinearity of silicon combined with the low nonlinear absorption in the mid-infrared is exploited to generate picosecond pulse based supercontinuum sources, optical parametric oscillators and wavelength translators connecting the telecommunication wavelength range and the mid-infrared.


Journal of The Electrochemical Society | 2003

Successful Selective Epitaxial Si1 − x Ge x Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications

Roger Loo; Matty Caymax; I. Peytier; Stefaan Decoutere; Nadine Collaert; Peter Verheyen; Wilfried Vandervorst; K. De Meyer

Si 1-x Ge x /Si heterostructures are useful for numerous device applications where device performance is improved by band offsets and/or increased carrier mobility. The use of selective epitaxial growth for the implementation of Si 1-x Ge x has some advantages compared to a nonselective growth process. However, some issues such as thickness nonuniformity (microloading on a micrometer scale and gas depletion on a wafer scale) and facet formation must be solved. In this paper, we give a detailed overview of our selective Si 1-x Ge x growth process in a standard production-oriented chemical vapor deposition system for Go contents between 0 and 32%. Our process allows layer deposition with no pattern dependence of the growth rate and Ge content (no microloading) and with a wafer scale layer nonuniformity that is better than the accuracy of the measurement techniques (∼2%). Facet formation was avoided by choosing the correct growth conditions and by preventing lateral growth over the mask material. Selective epitaxial layers did not show a degradation of photoluminescence characteristies. The layer quality is further demonstrated by the performance of Si 1-x Ge x heterojunction bipolar transistors (0.35 and 0.25 μm technology), and p-type Si 1-x Ge x heterojunction metal oxide semiconductor devices (effective gate length down to 70 nm).


Optical Materials Express | 2013

Silicon-based heterogeneous photonic integrated circuits for the mid-infrared

Günther Roelkens; Utsav Dave; Alban Gassenq; Nannicha Hattasan; Chen Hu; Bart Kuyken; François Leo; Aditya Malik; Muhammad Muneeb; Eva Ryckeboer; Sarah Uvin; Zeger Hens; Roel Baets; Yosuke Shimura; Federica Gencarelli; Benjamin Vincent; Roger Loo; Joris Van Campenhout; L. Cerutti; Jean Baptiste Rodriguez; E. Tournié; Xia Chen; Milos Nedeljkovic; Goran Z. Mashanovich; Li Shen; Noel Healy; Anna C. Peacock; Xiaoping Liu; Richard M. Osgood; W. M. J. Green

In this paper we present our recent work on mid-infrared photonic integrated circuits for spectroscopic sensing applications. We discuss the use of silicon-based photonic integrated circuits for this purpose and detail how a variety of optical functions in the mid-infrared besides passive waveguiding and filtering can be realized, either relying on nonlinear optics or on the integration of other materials such as GaSb-based compound semiconductors, GeSn epitaxy and PbS colloidal nanoparticles.


Applied Physics Letters | 2013

Germanium-on-silicon planar concave grating wavelength (de) multiplexers in the mid-infrared

Aditya Malik; Muhammad Muneeb; Yosuke Shimura; Joris Van Campenhout; Roger Loo; Günther Roelkens

Mid-infrared wavelength (de)multiplexers based on planar concave gratings (PCGs) fabricated on a germanium-on-silicon waveguide platform are presented. PCGs with two different types of gratings (flat facet and distributed bragg reflectors) are analyzed for both transverse electric (TE) and transverse magnetic (TM) polarizations. The insertion loss and cross talk for flat facet PCGs are found to be −7.6/−6.4 dB and 27/21 dB for TE/TM polarization. For distributed bragg reflector PCGs the insertion loss and cross talk are found to be −4.9/−4.2 dB and 22/23 dB for TE/TM polarization.


Applied Physics Letters | 2004

Tensely strained silicon on SiGe produced by strain transfer

D. Buca; B. Holländer; H. Trinkaus; S. Mantl; R. Carius; Roger Loo; Matty Caymax; H. Schaefer

An approach for the controlled formation of thin strained silicon layers based on strain transfer in an epitaxial Si∕SiGe∕Si(100) heterostructure during the relaxation of the SiGe layer is established. He+ ion implantation and annealing is employed to initiate the relaxation process. The strain transfer between the two epilayers is explained as an inverse strain relaxation which we modeled in terms of the propagation of the dislocations through the layers. Effcient strain buildup in the Si top layer strongly depends on the Si top layer thickness and on the relaxation degree of the SiGe buffer. 100% strain transfer was observed up to a critical thickness of the strained silicon layer of 8nm for a 150nm relaxed Si0.74Ge0.26 buffer.


Applied Physics Letters | 2010

Selective area growth of high quality InP on Si (001) substrates

Gang Wang; Maarten Leys; Roger Loo; Olivier Richard; Hugo Bender; Niamh Waldron; Guy Brammertz; J Dekoster; Wei-E Wang; Marc Seefeldt; Matty Caymax; Marc Heyns

In this work, we demonstrate the selective area growth of high quality InP layers in submicron trenches on exactly (001) oriented Si substrates by using a thin Ge buffer layer. Antiphase domain boundaries were avoided by annealing at the Ge surface roughening temperature to create additional atomic steps on the Ge buffer layer. The mechanism of Ge surface atomic step formation and the corresponding step density control method are illustrated. The elimination of antiphase boundaries from the optimized Ge buffer layer, together with the defect necking effect, yield defect-free top InP layers inside the trenches.


Journal of The Electrochemical Society | 2009

The Influence of the Epitaxial Growth Process Parameters on Layer Characteristics and Device Performance in Si-Passivated Ge pMOSFETs

Matty Caymax; Frederik Leys; Jerome Mitard; Koen Martens; Lijun Yang; Geoffrey Pourtois; Wilfried Vandervorst; Marc Meuris; Roger Loo

Recently, the best 65 nm Ge p-channel metal-oxide-semiconductor field-effect transistor (pMOSFET) performance has been reported with a standard Si complementary metal-oxide-semiconductor HfO 2 gate stack module. The Ge passivation is based on a thin, fully strained epitaxial Si layer grown on the Ge surface. We investigate in more detail how the device performance (hole mobility, I on , D it, V t , etc.) depends on the characteristics of this Si layer. We found that surface segregation of Ge through the Si layer takes place during the growth, which turns out to be determining for the interfacial trap density and distribution in the finalized gate stack. Based on a better understanding of the fundamentals of the Si deposition process, we optimize the process by switching to another Si precursor and lowering the deposition temperature. This results in a 4 times lower D it and improved device performance.

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Matty Caymax

Katholieke Universiteit Leuven

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Yosuke Shimura

Katholieke Universiteit Leuven

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Eddy Simoen

Katholieke Universiteit Leuven

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Geert Eneman

Katholieke Universiteit Leuven

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Hugo Bender

Katholieke Universiteit Leuven

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