Nian-Feng Tzeng

Distributing Hot-Spot Addressing in Large-Scale Multiprocessors

When a large number of processors try to access a common variable, referred to as hot-spot accesses in [6], not only can the resulting memory contention seriously degrade performance, but it can also cause tree saturation in the interconnection network which blocks both hot and regular requests alike. It is shown in [6] that even if only a small percentage of all requests are to a hot-spot, these requests can cause very serious performances problems, and networks that do the necessary combining of requests are suggested to keep the interconnection network and memory contention from becoming a bottleneck.

RFID-Based 3-D Positioning Schemes

This research focuses on RFID-based 3-D positioning schemes, aiming to locate an object in a 3-dimensional space, with reference to a predetermined arbitrary coordinates system, by using RFID tags and readers. More specifically, we consider a hexahedron which may be a shipping container, a storage room, or other hexahedral shape spaces. A number of RFID tags and/or readers with known locations are deployed as reference nodes. We propose two positioning schemes, namely, the active scheme and the passive scheme. The former scheme locates an RFID reader. For example, it may be employed to locate a mobile person who is equipped with an RFID reader or an object that is approached by an RFID reader. The passive scheme locates an RFID tag, which is attached to the target object. Both approaches are based on a Nelder-Mead nonlinear optimization method that minimizes the error objective functions. We have carried out analyses and extensive simulations to evaluate the proposed schemes. Our results show that both schemes can locate the targets with acceptable accuracy. The active scheme usually results in smaller errors and has a lower hardware cost compared to its passive counterpart. On the other hand, the passive scheme is more efficient when locating multiple targets simultaneously. The effectiveness of our proposed approaches is verified experimentally using the IDENTEC RFID kits.

An efficient submesh allocation strategy for mesh computer systems

A processor allocation strategy is proposed which can apply to any mesh system and recognize submeshes with arbitrary sizes at any location in a mesh system. The proposed strategy allocates a submesh of exactly the size requested by an incoming task, completely avoiding internal fragmentation. Because of its efficient allocation, this strategy exhibits better performance than an earlier allocation strategy based on the buddy principle. An efficient implementation of this strategy is presented. Extensive simulation runs were carried out to collect experimental performance measures of interest under different allocation schemes for comparison.<<ETX>>

Novel self-configurable positioning technique for multihop wireless networks

Geographic location information can effectively improve the performance (e.g., in routing or intelligent coordination) of large wireless networks. In this paper, we propose a novel self-configurable positioning technique for multihop wireless networks, based on a Euclidean distance estimation model and a coordinates establishment scheme. A number of nodes serve as the landmarks to establish a coordinates system. Specifically, any pair of landmarks estimate their Euclidean distance according to the shortest path length between them and establish the coordinates system by minimizing an error objective function. Other nodes in the network can accordingly contact the landmarks and determine their own coordinates. The proposed technique is independent of the Global Navigation Satellite Systems (GNSSs), and the established coordinates can be easily tuned to GNSS if at least one node in the network is equipped with GNSS receiver. Our simulation results show that the proposed self-configurable positioning technique is highly fault-tolerable to measurement inaccuracy and can effectively establish the coordinates for multihop wireless networks. More landmarks yield more accurate results. With the rectification of our Euclidean distance estimation model, four to seven landmarks are usually sufficient to meet the accuracy requirement in a network with hundreds of nodes. The computing time for coordinates establishment is in the order of milliseconds for a GHz CPU, acceptable for most applications in the mobile ad hoc networks as well as the sensor networks.

Grid-based approach for working node selection in wireless sensor networks

In this paper, we propose a grid-based working node (WN) selection approach for wireless sensor networks. Due to coverage redundancy, it is highly desirable to identify a minimum subset of sensors in a wireless sensor network to serve as WNs, while the remaining sensors are deactivated to save power and reduce potential interference. The basic idea of our solution approach is to represent the coverage of the sensors by a number of sample points, i.e., the intersection points of the established grid. A simple approximation algorithm and a linear programming method are employed to select as few sensors as possible to cover all sample points. In order to reduce the computational time, clusters are formed and WN selection is performed within each cluster. The performance of the proposed WN selection schemes is quantified and the tradeoff among accuracy, communication overhead and computational time is evaluated via analyses and simulations.

Allocating precise submeshes in mesh connected systems

We propose a new processor allocation strategy that applies to any mesh system and recognizes submeshes of arbitrary sizes at any locations in a mesh system. The proposed strategy allocates a submesh of exactly the size requested by an incoming task, completely avoiding internal fragmentation. Because of its efficient allocation, this strategy exhibits better performance than an earlier allocation strategy based on the buddy principle. An efficient implementation of this strategy is presented. Extensive simulation runs are carried out to collect experimental cost and performance measures of interest under different allocation schemes. >

Simultaneous multithreading-based routers

This work considers the use of an SMT (simultaneous multithreading) processor in lieu of the conventional processor(s) in a router and evaluates quantitatively the potential gains as a result. An SMT processor exploits the benefits of both ILP (instruction level parallelism) and TLP (thread-level parallelism), suitable for the next generation routers, in which an increased number of functions are to be implemented. The use of an SMT processor not only allows router functions to be decomposed into multiple threads but also designates separate threads to handle different incoming traffic streams of a router to exploit TLP, potentially attaining performance improvement. Additionally, an SMT processor may admit new router functions or added traffic streams relatively easily without compromising much existing performance levels, via including a new thread (or threads) to perform one newly added function or traffic stream. This router design appears to have better flexibility and adaptability. In order to assess the benefits of this design approach, we implemented three key router functions (i.e., packet header extraction, packet header manipulation, and longest-prefix matching) as threads using an SMT simulator (SMTSIM) for performance evaluation. The results of this router design approach are collected and compared with those of conventional routers.

Energy-efficient scheme for multiprocessor-based router linecards

In support of continuously increasing line rates and various Internet services, multiprocessor-based linecards have appeared in next-generation routers, significantly improving performance. However, this improvement has come at the expense of increased energy consumption, which tends to not only raise the operational and cooling costs, but also lower the reliability of the router. In this article, we present a simple and yet effective dynamic voltage scaling (DVS)-oriented scheme for energy-efficient operations of multiprocessor-based linecards. We prove that for a given task and a timing constraint, those processors in a linecard consume less energy when operating at the same voltage than operating at different voltages. Additionally, we derive the optimal configuration for minimal energy consumption in multiprocessor-based linecards and also show how it can be extended for general-purpose multiprocessor systems

A fast recognition-complete processor allocation strategy for hypercube computers

Fully recognizing various subcubes in a hypercube computer efficiently is addressed. A method with much less complexity than the multiple-GC strategy in generating the search space, while achieving complete subcube recognition, is proposed. This method is referred to as a dynamic processor allocation scheme because the search space generated is dependent on the dimension of the requested subcube dynamically. The basic idea lies in collapsing the binary tree representations of a hypercube successively so that the nodes which form a subcube but are distant are brought close to each other for recognition. The strategy can be implemented efficiently by using right rotating operations on the notations of the sets of subcubes corresponding to the nodes at a certain level of binary tree representations. Results of extensive simulation runs carried out to collect performance measures for different allocation strategies are discussed. It is shown that this strategy compares favorably in most situations with other known allocation schemes capable of achieving complete subcube recognition. >

Efficient resource placement in hypercubes using multiple-adjacency codes

While a certain resource in the hypercube may be shared by cube nodes to lower the cost, multiple copies of a shared resource often exist in the hypercube to reduce contention, and thus the potential delay, in fetching any shared copy. It is desirable that one employs as few resource copies as possible to ensure that every node is able to reach the resource in a given number of hops, achieving efficient resource placement. This placement method also keeps system performance degradation minimal after one resource copy becomes unavailable due to a fault. First, we consider placing multiple copies of a certain resource in a way that every cube node without the resource is adjacent to a specified number of resource copies. The use of our developed perfect and quasiperfect multiple-adjacency codes makes it possible to arrive at efficient solutions to this placement problem in a simple and systematic manner for an arbitrary hypercube. We then deal with the generalized resource placement in the hypercube such that every node without the resource can reach no less than a specified number of resource copies in no more than a certain number of hops, using as few resource copies as possible. Our placement results yield lowest potential access contention for a given number of resource copies (i.e., cost), particularly useful for large-scale hypercubes. >