Nicholas Waite

512

Single element 33×33 μm² InAs/GaSb superlattice light-emitting diodes (SLEDs) operating at 77 K with peak emission at approximately 4.6 μm are demonstrated. A peak radiance of 2.2 W/cm²/sr was measured corresponding to an apparent temperature greater than 1350 K within the 3-5 μm band. A 48 μm pitch, 512 × 512 individually addressable LED array was fabricated from a nominally identical SLED wafer, hybridized with a read-in integrated circuit, and tested. The array exhibited a pixel yield greater than 95%.

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We propose a novel continuous-time simultaneous-readout scheme for active imaging systems based on orthogonal modulation of photodetector signals. The superimposed-continuous-time approach presented here differs from the conventional scheduled-discrete-time scheme in that the photodetector signals are summed in a common bus and read concurrently. We show how that our proposed architecture may be advantageous, particularly in applications where bandwidth requirements for a time-multiplexed scheme are highly demanding. The active readout cell presented here is the kernel of the proposed orthogonal encoding architecture. We describe the cell operation principle, its properties and major design challenges. A 0.5-/spl mu/m CMOS test chip has been fabricated to demonstrate functionality of the readout architecture. Test results show it to be a viable option for highly-integrated active imaging systems.

512 Individually Addressable MWIR LED Arrays Based on Type-II InAs/GaSb Superlattices

The CVORG group at the University of Delaware is responsible for designing and developing a test platform for the operation and characterization of a 512×512 array of infrared LED emitters. This platform consists mainly of an integrated circuit responsible for driving current to the LEDs, a package to which the driver and LEDs can be mounted, and a cryogenic dewar used to run tests at 77K. The fabrication of the driver read-in integrated circuit, or RIIC, was completed using a 0.5μm CMOS process from OnSemiconductor. Because of the size of the array, stitching techniques were used to create the 3.3cm×3.3cm chip. The cryogenic package is a custom 6-layer printed circuit board (PCB) plated in a soft wire-bondable gold. Finally, modifications were made to the cryogenic dewar to allow us to properly interface with the RIIC.

0.5-/spl mu/m CMOS orthogonal encoding readout cell for active imaging systems

Fiber array optical systems that are used for free-space optical communications and phased laser beam projection applications depend on fast, closed-loop adaptive control to efficiently compensate for optical distortion caused by atmospheric turbulence. Current off-the-shelf systems are limited in performance, fiber array control channels, and flexibility. In this research project, we built a scalable and versatile platform for closed-loop controlling fiber-arrays with high update rate and rapid algorithm development. The controller platform consists of two parts: (I) an analysis and simulation software framework that is used for algorithm development and finding optimal parameters. Code written and simulated can then be directly ported to (II), a real-time hardware engine that can execute the algorithm in a real system and has the capability of controlling a large number of fiber arrays for testing and deployment in field conditions. The analysis and simulation software framework is used to simulate and predict how well the hardware will perform the implemented algorithm with a certain set of parameters and visualize the results of software or hardware runs. The optimized algorithms can be easily transferred back and forth to the hardware engine to run in real-time. The hardware platform is capable of standalone operation and is based on a System on chip (SoC) which has an ARM Central Processor Unit (CPU) and a floating-point Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), custom hardware modules that has large array of digital to analog convertors (DACs) and amplifiers for controlling fiber arrays, and another custom hardware module that has amplified ADC channels for reading back the quality metric value. Test results from the prototype system with 19 DAC channels and two analog to digital convertor (ADC) channels are presented and compared with simulated results.

System for driving 2D infrared emitter arrays at cryogenic temperatures

This research project aims to provide a software framework to test and simulate optimization algorithms for a phase locked fiber laser array. The adaptive phase coherent fiber laser array system is a prominent innovation in the areas of optical communications and directed energy projection [1][2]. In comparison with a monolithic large aperture system, the phase locked array exhibits dramatic improvements in cost, size, and energy density at the center of the beam [2].

Modular adaptive phased-locked fiber array controller platform

The demand for high-speed and/or high-temperature infrared (IR) scene projectors has led to the development of systems based on IR light-emitting-diode (LED) arrays. Using mid-wave (3--5 μm) superlattice LED arrays, a 512 × 512 pixel scene projection system operating at 100 Hz has been fully developed. These LEDs, flip-chip bonded to a read-in integrated circuit, display temperatures of up to 1350 K when cooled to liquid nitrogen temperature (77 K). Using custom drive electronics and packaging, the array has been nonuniformity corrected (NUCed) and has survived hundreds of hours of operation at multiple facilities. This system is fully configurable by the user and has a digital visual interface to display content.

Algorithm development, optimization, and simulation framework for a phase-locking fiber laser array

With increased focus on intermittent renewable energy sources such as wind turbines and photovoltaics, there comes a rising need for large-scale energy storage. The vehicle to grid (V2G) project seeks to meet this need using electric vehicles, whose high power capacity and existing power electronics make them a promising energy storage solution. This paper will describe a charging system designed by the V2G team that facilitates selective charging and backfeeding by electric vehicles. The system consists of a custom circuit board attached to an embedded linux computer that is installed both in the EVSE (electric vehicle supply equipment) and in the power electronics unit of the vehicle. The boards establish an in-band communication link between the EVSE and the vehicle, giving the vehicle internet connectivity and the ability to make intelligent decisions about when to charge and discharge. This is done while maintaining compliance with existing charging protocols (SAEJ1772, IEC62196) and compatibility with standard “nonintelligent” cars and chargers. Through this system, the vehicles in a test fleet have been able to successfully serve as portable temporary grid storage, which has implications for regulating the electrical grid, providing emergency power, or supplying power to forward military bases.