Fouad Kiamilev

Description and evaluation of the FAST-Net smart pixel-based optical interconnection prototype

The design, packaging approach, and experimental evaluation of the free-space accelerator for switching terabit networks (FAST-Net) smart-pixel-based optical interconnection prototype are described. FAST-Net is a high-throughput data-switching concept that uses a reflective optical system to globally interconnect a multichip array of smart pixel devices. The three-dimensional optical system links each chip directly to every other with a dedicated bidirectional parallel data path. in the experiments, several prototype smart-pixel devices were packaged on a common multichip module (MCM) with interchip registration accuracies of 5-10 /spl mu/m. The smart-pixel arrays (SPAs) consist of clusters of oxide-confined vertical-cavity surface-emitting lasers and photodetectors that are solder bump-bonded to Si integrated circuits. The optoelectronic elements are arranged within each cluster on a checkerboard pattern with 125-/spl mu/m pitch. The experimental global optical interconnection module consists of a mirror and lens array that are precisely aligned to achieve the required interchip parallel connections between up to 16 SPAs. Five prototype SPAs were placed on the MCM to allow the evaluation of a variety of interchip links. Measurements verified the global link pattern across several devices on the MCM with high optical resolution and registration. No crosstalk between adjacent channels was observed after alignment. The I/O density and efficiency results suggest that a multi-terabit switch module that incorporates global optical interconnection to overcome conventional interconnection bottlenecks is feasible.

Initial explorations on design pattern energy usage

As the use of computers has grown, so too has concern about the amount of power they consume. Data centers, for example, are limited in scalability as they struggle with soaring energy costs from many large companies relying on fast, reliable, and round-the-clock computing services. On large-scale computing clusters, like data centers, even a small drop in power consumption can have large effects. Across computing contexts, reducing power consumed by computers has become a major focus. In this paper, we present a new approach for mapping software design to power consumption and present empirical results of the approach on different software implementations. In particular, we compare the power profiles of software using design patterns against software not using design patterns as a way to explore how high-level design decisions affect an applications energy usage. We show how mappings between software design and power consumption profiles can provide software designers and developers with useful information about the power behavior of the software they are developing. The goal is for software engineers to use this information in designing and developing more energy efficient solutions.

Cascaded electro-optic scanning of laser light over large angles using domain microengineered ferroelectrics

We present a device concept based on cascaded electro-optic deflection in a domain microengineered ferroelectric chip. In our design, large deflection angles are achieved by cascading several smaller scanners in a single ferroelectric chip, such that each successive scanner stage builds upon the deflection of the previous stage. We demonstrate the basic concept using a two-stage device fabricated in a single crystal wafer of ferroelectric LiTaO3. By operating the device using a specially designed programmable multichannel driver that provides ±1.1 kV per stage, a total scan angle of 25.4° at 5 kHz was demonstrated. Even larger angles of deflection are possible with additional scanner stages.

Multichip free-space global optical interconnection demonstration with integrated arrays of vertical-cavity surface-emitting lasers and photodetectors.

The experimental optical interconnection module of the Free-Space Accelerator for Switching Terabit Networks (FAST-Net) project is described and characterized. Four two-dimensional (2-D) arrays of monolithically integrated vertical-cavity surface-emitting lasers (VCSELs) and photodetectors (PDs) were designed, fabricated, and incorporated into a folded optical system that links a 10 cm x 10 cm multichip smart pixel plane to itself in a global point-to-point pattern. The optical system effects a fully connected network in which each chip is connected to all others with a multichannel bidirectional data path. VCSELs and detectors are arranged in clusters on the chips with an interelement spacing of 140 microm. Calculations based on measurements of resolution and registration tolerances showed that the square 50-microm detector in a typical interchip link captures approximately 85% of incident light from its associated VCSEL. The measured optical transmission efficiency was 38%, with the losses primarily due to reflections at the surfaces of the multielement lenses, which were not antireflection coated for the VCSEL wavelength. The overall efficiency for this demonstration is therefore 32%. With the measured optical confinement, an optical system that is optimized for transmission at the VCSEL wavelength will achieve an overall efficiency of greater than 80%. These results suggest that, as high-density VCSEL-based smart pixel technology matures, the FAST-Net optical interconnection concept will provide a low-loss, compact, global interconnection approach for high bisection-bandwidth multiprocessor applications in switching, signal processing, and image processing.

The AMOEBA chip: an optoelectronic switch for multiprocessor networking using dense-WDM

We present AMOEBA: a single-chip asynchronous multiprocessor optoelectronic bit-sliced arrayed crossbar switch intended to provide switched interconnection between multiple processors in a distributed computing environment. AMOEBA relies on optoelectronic-VLSI integration, free-space optical interconnects, and wavelength-and-space-division multiplexed networking on single-mode fiber. We report the implementation and testing of a first generation, 16-channel prototype of the switch and a compact opto-mechanical transceiver package that accomplishes the free-space-to-fiber interfacing.

Kernel-based sparse representation for gesture recognition

In this paper, we propose a novel sparse representation based framework for classifying complicated human gestures captured as multi-variate time series (MTS). The novel feature extraction strategy, CovSVDK, can overcome the problem of inconsistent lengths among MTS data and is robust to the large variability within human gestures. Compared with PCA and LDA, the CovSVDK features are more effective in preserving discriminative information and are more efficient to compute over large-scale MTS datasets. In addition, we propose a new approach to kernelize sparse representation. Through kernelization, realized dictionary atoms are more separable for sparse coding algorithms and nonlinear relationships among data are conveniently transformed into linear relationships in the kernel space, which leads to more effective classification. Finally, the superiority of the proposed framework is demonstrated through extensive experiments.

Photonic page buffer based on GaAs multiple-quantum-well modulators bonded directly over active silicon complementary-metal-oxide-semiconductor (CMOS) circuits

We present a 2-kbit, 50-Mpage/s, photonic first-in, first-out page buffer based on gallium arsenide/aluminium-gallium arsenide multiple-quantum-well diodes that are flip-chip bonded to submicrometer silicon complementary-metal-oxide-semiconductor circuits. This photonic chip provides nonvolatile storage (buffering), asynchronous-to-synchronous conversion, bandwidth smoothing, tolerance to jitter or skew, spatial format conversion, wavelength conversion, and independent flow control for the input and the output channels. It serves as an interface chip for parallel-accessed optical bit-plane data. It represents the first smart-pixel array that accomplishes the vertical integration of multiple-quantum-well modulators and detectors directly over active silicon VLSI circuits and provides over 340 transistors per optical input-output. Results from high-speed single-channel testing and real-time array operation of the photonic page buffer are reported.

CMOS static RAM chip with high-speed optical read and write

We present the first demonstration of a dense VLSI RAM technology with high-speed optical read and optical write capability. The CMOS-based Static-RAM technology is capable of parallel optical access with read/write speeds limited by the native RAM access times. We fabricated a 2/spl times/2 mm optoelectronic-VLSI test chip incorporating 800-b storage and 200 optical I/O based on the hybrid integration of GaAs-AlGaAs MQW modulators on CMOS. Results from the photonic-SRAM test-chip confirm 6.2 ns read and 8-ns write capability.

A high-speed 32-channel CMOS VCSEL driver with built-in self-test and clock generation circuitry

This paper describes the design, electrical, and optical test results for a high-speed 32-channel CMOS vertical-cavity surface emitting laser (VCSEL) driver integrated circuits with built-in self-test and clock generation circuitry. The circuit design and silicon parts are available to the research community through the Consortium for Optical and Optoelectronic Technologies in Computing (CO-OP) and the Optoelectronics Industry Association (OIDA). This device is specifically targeted at users building VCSEL-based smart photonic system demonstrators. A ten-channel version of this driver chip is also available with the same functionality and performance.

Optoelectronic multichip module integration for chip level optical interconnects

We have integrated an 850-nm vertical-cavity surface-emitting laser (VCSEL), its driver, and a diffractive lenslet array onto a single substrate to produce an integrated optoelectronic multichip module for signal fan-out and distribution. The diffractive element performs optical fan-out of the output beam from the VCSEL into an array of focused spots at a plane 1, 416 /spl mu/m from the surface of the VCSEL. This corresponds to 160 /spl mu/m from the surface of the diffractive lens. System design, fabrication, integration, and experimental characterization is presented.