Jorge Garcia

0.5-/spl mu/m CMOS orthogonal encoding readout cell for active imaging systems

We propose a novel continuous-time simultaneous-readout scheme for active imaging systems based on orthogonal modulation of photodetector signals. The superimposed-continuous-time approach presented here differs from the conventional scheduled-discrete-time scheme in that the photodetector signals are summed in a common bus and read concurrently. We show how that our proposed architecture may be advantageous, particularly in applications where bandwidth requirements for a time-multiplexed scheme are highly demanding. The active readout cell presented here is the kernel of the proposed orthogonal encoding architecture. We describe the cell operation principle, its properties and major design challenges. A 0.5-/spl mu/m CMOS test chip has been fabricated to demonstrate functionality of the readout architecture. Test results show it to be a viable option for highly-integrated active imaging systems.

High-gain 0.8-μm CMOS readout integrated circuit for FM/CW line-imaging ladar

We are engaged in research of readout techniques and development of readout integrated circuits for active and active/passive imaging systems under development at the Army Research Laboratory. Here we report a readout integrated circuit chip designed for ARLs FM/cw line-imaging ladar. The readout chip consists of two 1 x 8 element arrays of high-gain amplifiers that convert the input photocurrent signal to a voltage signal appropriate for digitization. Each amplifier consists of a transimpedance input stage op amp followed by a voltage-gain op amp and output buffer. The input transimpedance stage is a CMOS operational amplifier designed for a transimpedance gain of almost 1 MΩ. The voltage amplifier of stage two, also an operational amplifier, is designed to provide additional gain of about 150. Test chips have been fabricated and are being tested. The initial measured transimpedance gain of the entire amplifier cell is 130 MΩ. We discuss the chip design, physical layout, and initial performance test results.

Mixed-signal equalization architectures for printed circuit board channels

This paper develops mixed-signal equalization solutions for gigabit communications in printed circuit boards (PCBs). The PCB channel, composed by vias and interconnects, distorts, and produces signal reflections that deteriorate quality of high-speed data transmission. Analog signal processing architectures are necessary to combat the inter-symbol interference effects introduced by the channel since high-speed analog-to-digital conversion is a very expensive solution. A novel system implementation and circuit-level architecture that performs mixed-signal feedforward (FF) and feedback (FB) equalization in the transmit end is introduced. System level simulations show how this combined FF-FB transmit equalizer outperforms the conventional pre-emphasis structures presented in previous works, with a reasonable compromise in circuit area. In addition, practical constraints like the maximum output signal, the filter coefficients spread, and the sensitivity of the solution with respect to components variation are presented, demonstrating the robustness of the proposed architecture.

0.18 μm CMOS fully differential CTIA for a 32x16 ROIC for 3D ladar imaging systems

We describe a 2-D fully differential Readout Integrated Circuit (ROIC) designed to convert the photocurrents from an array of differential metal-semiconductor-metal (MSM) detectors into voltage signals suitable for digitization and post processing. The 2-D MSM array and CMOS ROIC are designed to function as a front-end module for an amplitude modulated/continuous time AM/CW 3-D Ladar imager under development at the Army Research Laboratory. One important aspect of our ROIC design is scalability. Within reasonable power consumption and photodetector size constraints, the ROIC architecture presented here scales up linearly without compromising complexity. The other key feature of our ROIC design is the mitigation of local oscillator coupling. In our ladar imaging application, the signal demodulation process that takes place in the MSM detectors introduces parasitic radio frequency (rf) currents that can be 4 to 5 orders of magnitude greater than the signal of interest. We present a fully-differential photodetector architecture and a circuit level solution to reduce the parasitic effect. As a proof of principle we have fabricated a 0.18 μm CMOS 32x16 fully differential ROIC with an array of 32 correlated double sampling (cds) capacitive transimpedance amplifiers (CTIAs), and a custom printed circuit board equipped to verify the test chip functionality. In this paper we discuss the fully differential IC design architecture and implementation and present the future testing strategy.

A quad 1/spl times/16 CMOS ROIC with fully differential CTIA-CDS for orthogonally modulated 2-D active imaging systems

In order to improve the system sensitivity and to minimize the effects of electronic offset and power supply noise, a fully differential architecture has been implemented. Thus, at the end of each row, the differential row busses are fed to fully differential capacitive transimpedance amplifiers (CTIAs) that take care of the current-to-voltage conversion. Their outputs are driven externally for digitization and post processing. The remaining of this paper describes the design, fabrication and prototype testing of the fully differential CTIA amplifier

Class AB readout cell designed to reduce the noise of a concurrent continuous-time readout architecture for imaging systems

An alternative, class AB configuration of a proven class A readout cell for active/passive imaging systems is presented. Comparison between the two approaches shows that class AB circuit lowers power consumption and reduces noise by a factor of 3 while using nearly equal chip area. On the other hand, class AB has lower bandwidth because it operates at lower bias currents. A 0.5μm CMOS test chip that includes both types of readout circuits has been designed, fabricated and is currently being tested. Simulation results, using readout circuits from this test chip, are used to compare the two configurations.

Demonstration of CMOS readout technique with pixel-level code modulation for 2-D active imaging

Proof-of-principle experiments of the CMOS readout technique with pixel-level code modulation for 2-D active imaging are demonstrated. The encoding readout technique can be advantageous for passive imaging systems, such as long-wave infrared imagers where there is a very large background flux. Another potential application for the encoding technique is high-speed passive imaging, particularly for applications that do not require extremely high amplitude resolution.