Roberto Nonis

A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS

State of the art digital PLLs can be divided in two categories, depending on the implementation of the digital phase detector. Digital clocking and wireline applications mostly use a Bang-Bang detector (BBPLLs) [1–3], offering very low jitter values in integer-N mode but not supporting fractional-N synthesis, which is desirable to implement, i.e., spread spectrum clocking (SSC) for EMI reductions. Wireless applications implement time to digital converters (TDC) [4–6] which allow fractional-N synthesis, but require high architecture complexity, need calibration routines for period normalization, and introduce analog limitations that a digital PLL should be intended to eliminate.

digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture

This paper introduces a novel architecture of digital PLL. The goal of this architecture is to reach low jitter, fractional operation, and FSK modulation capability with low architecture complexity for small area, low power, and minimal design effort. The architecture is based on the bang-bang phase detector, so that usage of time-to-digital-converter circuits is avoided, with no need for any background calibration. The key enabling blocks are a phase interpolator-based exact fractional frequency divider, and a multi-output bang-bang phase detector. The prototype implemented in 130 nm reaches 1-psrms absolute jitter while operating in integer mode and 1.9 psrms absolute jitter while operating in full fractional mode, with an output frequency of 1 GHz and reference frequency of 25 MHz, consuming 7.4 mW from a supply of 1.3 V. FSK modulation of the 1 GHz carrier up to 300 kbps with a frequency deviation of ±150 kHz is also implemented and measured .

Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs

This paper presents a modular and comprehensive nonlinear time-domain behavioral model for phase-locked loops (PLLs) that are suitable for analyzing the impact on the output signal of the noise contribution and nonidealities of the constituent building blocks. The model building blocks are described by Simulink submodels and can be configured to implement different PLL topologies. Postprocessing of the PLL output provides the PLL phase noise and spur-to-carrier-ratio performances. The calculated phase-noise spectra are compared with those obtained with the well-known linear model and with measurements. To show the flexibility of this approach, many case studies are reported; among them, the analysis of the spurs due to charge pump mismatch and the transient phase noise, and spurs performances of a PLL featuring a dual control of the voltage-controlled oscillator.

A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider

In the field of digital PLLs, there is a trend to find alternatives to time-to-digital converter(TDC)-based architectures [1] to avoid significant complexity and power overhead due to such a critical building block [2-4]. Architectures based on bang-bang phase detectors are very attractive for their low-jitter, low-power capabilities, but are limited to integer-N operation by nature. Solutions that merge the key performance of the bang-bang architecture with fractional-N operation as in [3] are needed in order to turn the bang-bang digital PLLs into real alternatives to TDC-based PLLs.

Design of a transmitter for high-speed serial interfaces in automotive micro-controller

This work reports about the system level design of a transmitter for the next generation of High-Speed Serial Interfaces (HSSI) to be implemented in a micro-controller for automotive Electronic Control Unit (ECU) applications, pushing the transmission speed up to 10 Gbps over a 10cm long cable. A voltage mode architecture is selected for low power considerations. We focus our analysis here on the system-level implementation of Feed-Forward Equalization as an FIR filter consisting of different transmitter slices driven by different bits in the data sequence. We consider different data rates and number of taps and analyze how the performance of the equalizer is affected by the quantization of the values of the taps in the practical implementation of the FIR filter.

Wideband chirp generation techniques in digital phase-locked loops

In this paper in-depth analysis and comparison of two popular FM techniques, namely, two-point modulation and pre-emphasis of the modulation signal are presented. Both modulation enhancement techniques were implemented in the time domain model of an all-digital phase-locked loop (ADPLL). Their performance is evaluated based on Matlab simulations for different type of chirps. Obtained results show that chirps with the period of 0.1ms and peak-to-peak bandwidth of 1GHz can be generated with linearity better than 1% by employing either of these techniques. Additionally, advantages of two-point modulation with respect to ADPLL building block requirements are demonstrated.

PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique

This paper analyzes and compares two popular methods to widen the modulation bandwidth of a phase-locked loop, i.e., the pre-emphasis and the two-point injection technique. The analysis reveals that both architectures have the same sensitivity to gain errors and nonlinearity in the loop, though, compared with the pre-emphasis, the two-point injection scheme features less sources of error and does not require a phase detector with wide range and tight linearity requirements. The verification of the analysis as well as the comparison of the two modulation techniques is carried out on an accurate time-domain model of a 60-GHz digital phase-locked loop, taken as a case study and used to generate wideband chirp signals for a radar system.

A precision 140MHz relaxation oscillator in 40nm CMOS with 28ppm/°C frequency stability for automotive SoC applications

The need for high-frequency, low-power, wide temperature range, precision on-chip reference clock generation makes relaxation oscillator topology an attractive solution for various automotive applications. This paper presents for the first time a 140MHz relaxation oscillator with robust-against-process-variation temperature compensation scheme. The high-frequency relaxation oscillator achieves 28 ppm/°C frequency stability over the automotive temperature range from −40 to 175°C. The circuit is fabricated in 40nm CMOS technology, occupies 0.009 mm2 and consumes 294µW from 1.2V supply.

Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars

The need for low-noise, highly-linear, programmable chirp generators makes digital phase-locked loops (DPLLs) an attractive solution for radar sensors. This paper presents a general analysis and comparison of the two main techniques enabling wideband frequency modulation (FM) in PLLs, namely the two-point injection and the pre-emphasis. It is shown that while the two topologies are equivalent in term of mismatch error suppression, the required input range for the time-to-digital converter (TDC) is substantially lower in the two-point injection scheme, thus relaxing the TDC power consumption and linearity.

F2: High-performance frequency generation for wireless and wireline systems

Frequency generation equips nearly all electronic systems and is a critical performance factor for many of them. This forum focuses on wireless and wireline systems, which demand high performance clocks, and looks for synergies between them. The topics cover both fundamental techniques and specific applications. State-of-the-art techniques will be explored in depth, such as high-FOM VCOs, digital-to-time converters, sampling phase-detectors, synthesizable and digital PLLs. Attention will also be on booming applications, such as high-speed wireline, FMCW radar, mm-wave and THz. The forum aims at bringing together the contemporary top interests with added value and sowing seeds to inspire the future.