Thibaut David

Patterning of silicon nitride for CMOS gate spacer technology. I. Mechanisms involved in the silicon consumption in CH3F/O2/He high density plasmas

A loss of silicon in active source/drain regions of CMOS transistors can be observed during nitride spacer etch processes, employing CH3F/O2/He based chemistries in high density plasmas. This phenomenon, the so-called “silicon recess”, is a key criterion for the subsequent steps involved in the transistor fabrication process. In this work, the authors compare two CH3F/O2/He spacer etch processes typically used in industry. The mechanism for high Si3N4/Si selectivity is identified as the creation of a SiOxFy passivation layer, generated at the silicon surface. Using in situ ellipsometry and angle resolved x-ray photoelectron spectroscopy, the authors demonstrate that the oxidized layer which leads to silicon recess is driven by the ion energy. Moreover, in the case of high ion energy processes, implanted carbon has been identified under the SiOxFy passivation layer.

Impact of low-k structure and porosity on etch processes

The fabrication of interconnects in integrated circuits requires the use of porous low dielectric constant materials that are unfortunately very sensitive to plasma processes. In this paper, the authors investigate the etch mechanism in fluorocarbon-based plasmas of oxycarbosilane (OCS) copolymer films with varying porosity and dielectric constants. They show that the etch behavior does not depend on the material structure that is disrupted by the ion bombardment during the etch process. The smaller pore size and increased carbon content of the OCS copolymer films minimize plasma-induced damage and prevent the etch stop phenomenon. These superior mechanical properties make OCS copolymer films promising candidates for replacing current low-k dielectric materials in future generation devices.

Patterning of porous SiOCH using an organic mask: Comparison with a metallic masking strategy

The etching of sub-100-nm porous dielectric trenches has been investigated using an organic mask. The etching process that is performed in an oxide etcher is composed of three steps: a thin dielectric antireflective coating (DARC) layer (silicon containing layer) is etched in the first step, the organic mask [carbon-based layer (CL)] is opened in the second step, and the dielectric layer is etched in the last step. The DARC layer is open in a fluorocarbon-based plasma (CF4∕Ar∕CH2F2) and the main critical dimension issue is the critical dimension control of the trench, which can be adjusted by controlling the amount of polymer generated by the etching chemistry (% of CH2F2). The CL is etched using NH3 based plasmas, leading to straight trench profiles. For dielectric patterning, the etch process results from a delicate trade-off between passivation layer thickness and mask faceting. This is driven by the polymerizing rate of the plasma (% of CH2F2) which controls the trench width. Using an optimized etchin...

Residue growth on metallic-hard mask after dielectric etching in fluorocarbon-based plasmas. I. Mechanisms

This work focuses on the formation of residues that grow on a metallic-hard mask after etching of porous low-k materials in fluorocarbon-based plasmas. The residue growth, which is dependent on the air exposure time after etching, causes line and via opens that strongly impact the yield performance. The different elements which could play a role in the chemical reactions have been clarified. The authors have demonstrated that in their experimental conditions, after fluorocarbon etching and air exposure, the oxidized titanium nitride reacts with fluorhydric acid to form metallic salts. This is a reaction between fluorine from the reactive layer formed on titanium nitride and hydrogen coming from the atmosphere. This reaction is all the more fast because the titanium nitride is oxidized.

Impact of Downstream Ash Plasmas on Ultra Low-k Materials

Introduction Next generation integrated circuits require novel materials with a dielectric constant lower than 2.5. To lower the dielectric constant, porous Methyl-SilsesQuioxane (MSQ) materials are introduced with a k value of about 2.2. The integration of these materials presents new processing issues, mainly due to a change in material density caused by the presence of the pores [1]. For instance, ash treatments for photoresist and residues removal are critical steps leading to dielectric properties modifications [2]. In this paper, we present the structure and properties modifications of porous and non-porous MSQ films under various downstream ash processes.

Etching process scalability and challenges for ULK materials

With the scaling down of integrated circuit devices, a constant effort is needed to improve the patterning technologies of interconnect stacks using either the metallic masking strategy or the organic masking strategy. Critical dimensions and profile control, plasma-induced damages (modifications, post etch residues, porous SiOCH roughening) are the key challenges to successfully pattern dual damascene porous SiOCH structures. We have compared the patterning performances of both masking strategies in terms of profile control. One of the main challenges is to optimize the plasma processes to minimize the dielectric sidewall modification. This has been achieved by using optimized or new characterization techniques such as scatterometric porosimetry, infrared spectroscopy, x-ray photoelectron spectroscopy.

Interaction Plasma/Dielectric

For the fabrication of interconnect structures, porous low-k dielectrics are exposed to various plasma processes during etching, during post-etch treatments used to remove carbon-based masks and during treatment surfaces. We will describe here the main plasma processes used for the integration of low-k films, focusing on plasma surface interaction for methylsilsesquioxane (MSQ) films (porous and non-porous SiOCH). When not mentioned, the film is deposited by plasma enhanced chemical vapor deposition (PECVD).

Low-k Integration Using Metallic Hard Masks

For the 45 nm interconnect technology node, porous dielectric materials (p-SiOCH) have been introduced, leading to complex integration issues due to their high sensitivity upon FC etching and ashing plasma exposure [1, 2]. Thanks to Metallic hard mask (MHM) integration high selectivities towards dielectric materials (>100:1) can be reached and minimizes exposure of p-SiOCH films to ashing plasmas. However MHM such as TiN generates other issues such as i) metal contamination in the patterned structures and ii) growth of metal based residues on the top of the hard mask [3, 4, 5]. The residues growth, which is air exposure time dependent, directly impacts the yield performance with the generation of via and line opens [.

Study of Resist Strip Chemistries for Ultra Low-k/Cu Interconnect

New generation of integrated circuits requires the introduction of ultra low-k dielectric material (k < 2.5) to reduce the RC delay. One of the challenges in integrating these ultra low-k materials is the susceptibility of porous dielectric materials to the post etch resist stripping and residue clean processes. There have been studies comparing the effect of oxidization and reducing chemistries to the ultra low-k materials in a conventional asher [1]. There has also been report on the approach of using directional ashing to avoid damage to the ultra low-k materials [2]. In order to gain further understanding regarding the effect of oxidizing vs. reducing chemistries, ion vs. radicals, pressure and temperature to the low-k materials (both dense and porous), we have started a comprehensive study to find answers to these questions. This paper is to report our initial data from this effort.