Nicolas Loubet

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at Lg=12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1-4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1-4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.

Strain, stress, and mechanical relaxation in fin-patterned Si/SiGe multilayers for sub-7 nm nanosheet gate-all-around device technology

Pre-strained fin-patterned Si/SiGe multilayer structures for sub-7u2009nm stacked gate-all-around Si-technology transistors that have been grown onto bulk-Si, virtually relaxed SiGe, strained Silicon-On-Insulator, and compressive SiGe-On-Insulator were investigated. From strain maps with a nanometer spatial resolution obtained by transmission electron microscopy, we developed 3D quantitative numerical models describing the mechanics of the structures. While elastic interactions describe every other system reported here, the patterning on the compressive SiGe-On-Insulator substrate that is fabricated by Ge-condensation results in relaxation along the semiconductor/insulator interface, revealing a latent plasticity mechanism. As a consequence, Si layers with a uniaxial stress of 1.4u2009GPa are obtained, bringing fresh perspectives for strain engineering in advanced devices. These findings could be extended to other semiconductor technologies.

Highly-selective superconformai CVD Ti silicide process enabling area-enhanced contacts for next-generation CMOS architectures

We investigate a novel Ti Chemical Vapor Deposition (CVD Ti) technique for source/drain and trench contact silicidation. This work is a first demonstration of a highly selective, superconformal Ti process that exhibits a low p-type CVD Ti/SiGe:B contact resistivity (pc) down to 2.1×10⁻⁹ Ω.cm² (a 40% reduction vs. PVD Ti), matching the lowest published values [1-5]. A competitive n-type CVD Ti/Si:P with a ρ<inf>c</inf> at 2.6×10⁻⁹ Ω.cm² is measured. We demonstrate up to 90% superconformality for this process, with a tunnel silicidation at lengths up to 500nm, showing an exceptional selectivity to oxide. This process is an enabler for the next generation of area-enhanced contact CMOS architectures.

Materials characterization for process integration of multi-channel gate all around (GAA) devices

Multi-channel gate all around (GAA) semiconductor devices march closer to becoming a reality in production as their maturity in development continues. From this development, an understanding of what physical parameters affecting the device has emerged. The importance of material property characterization relative to that of other physical parameters has continued to increase for GAA architecture when compared to its relative importance in earlier architectures. Among these materials properties are the concentration of Ge in SiGe channels and the strain in these channels and related films. But because these properties can be altered by many different process steps, each one adding its own variation to these parameters, their characterization and control at multiple steps in the process flow is crucial. This paper investigates the characterization of strain and Ge concentration, and the relationships between these properties, in the PFET SiGe channel material at the earliest stages of processing for GAA devices. Grown on a bulk Si substrate, multiple pairs of thin SiGe/Si layers that eventually form the basis of the PFET channel are measured and characterized in this study. Multiple measurement techniques are used to measure the material properties. In-line X-Ray Photoelectron Spectroscopy (XPS) and Low Energy X-Ray Fluorescence (LE-XRF) are used to characterize Ge content, while in-line High Resolution X-Ray Diffraction (HRXRD) is used to characterize strain. Because both patterned and un-patterned structures were investigated, scatterometry (also called optical critical dimension, or OCD) is used to provide valuable geometrical metrology.

An analysis of stress evolution in stacked GAA transistors

We used Finite Element Method to evaluate the stress evolution along a FEOL integration in Gate-All-Around transistors of stacked channels configuration. Hypothesis are done about the materials behavior and dimensions for 5 nm node to evaluate the upper and lower stress limits due to source and drain stressor effect. For the most probable configuration, slightly tensile Si channels are obtained either for pMOS and nMOS. Alternative solutions for stressing the channel in NS configuration would be essential.

Density scaling beyond the FinFET: Architecture considerations for gate-all-around CMOS

The promise of improved electrostatics and the ability to increase the amount of effective width (Weff) available in a given device footprint drove the semiconductor industry from planar CMOS transistors to the FinFET transistor starting at the 22 nm node. Numerous manufacturers are in large-scale production of 16 and 14 nm node FinFET technologies and there is no indication that a change in device architecture is planned for the 10 or 7 nm nodes. Looking beyond 7 nm, the scaling challenges of the FinFET are expected to increase dramatically. In particular, continued scaling of the fin width and fin pitch may reach a physical limit due to a combination of quantum effects, patterning process realities and contact architecture limitations. It is well known that gate-all-around (GAA) devices demonstrate improved electrostatics over double or triple-gated FinFET devices. In view of the impending difficulties occasioned by FinFET scaling, it is necessary to take a critical look at the possibility of a GAA CMOS device technology. In this paper, I will explore this topic by presenting relevant TCAD and experimental work on single and stacked GAA devices. The TCAD illustrates that a properly designed stacked GAA device architecture can show superior performance over a scaled FinFET reference. I will conclude by presenting experimental work to substantiate this claim.

Inline monitoring of SiGe strain relaxed buffers (SRBs) using high-resolution X-ray diffraction: AM: Advanced metrology

We describe the use of high resolution X-ray diffraction (HRXRD) for inline metrology of strain relaxed buffer (SRB) layers and epitaxial layers grown thereon. The use of SRBs as a virtual substrate is a promising candidate for advanced CMOS logic at the 7 nm technology node and presents some unique challenges to traditional HRXRD measurements. To overcome these challenges, reciprocal space maps (RSMs) were employed to characterize different films on SRBs. We discuss the measurement strategies and recent improvements to X-ray metrology tools that enable these measurements for inline process control. Furthermore, advances in the automated data extraction and analysis are introduced.

Advanced in-line optical metrology of sub-10nm structures for gate all around devices (GAA)

Gate-all-around (GAA) nanowire (NW) devices have long been acknowledged as the ultimate device from an electrostatic scaling point of view. The GAA architecture offers improved short channel effect (SCE) immunity compared to single and double gate planar, FinFET, and trigate structures. One attractive proposal for making GAA devices involves the use of a multilayer fin-like structure consisting of layers of Si and SiGe. However, such structures pose various metrology challenges, both geometrical and material. Optical Scatterometry, also called optical critical dimension (OCD) is a fast, accurate and non-destructive in-line metrology technique well suited for GAA integration challenges. In this work, OCD is used as an enabler for the process development of nanowire devices, extending its abilities to learn new material and process aspects specific to this novel device integration. The specific metrology challenges from multiple key steps in the process flow are detailed, along with the corresponding OCD solutions and results. In addition, Low Energy X-Ray Fluorescence (LE-XRF) is applied to process steps before and after the removal of the SiGe layers in order to quantify the amount of Ge present at each step. These results are correlated to OCD measurements of the Ge content, demonstrating that both OCD and LE-XRF are sensitive to Ge content for these applications.