Nicolas Veyrat-Charvillon

Carry Prediction and Selection for Truncated Multiplication

This paper presents an error compensation method for truncated multiplication. From two n-bit operands, the operator produces an n-bit product with small error compared to the 2n-bit exact product. The method is based on a logical computation followed by a simplification process. The filtering parameter used in the simplification process helps to control the trade-off between hardware cost and accuracy. The proposed truncated multiplication scheme has been synthesized on an FPGA platform. It gives a better accuracy over area ratio than previous well-known schemes such as the constant correcting and variable correcting truncation schemes (CCT and VCT)

Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of x

This paper presents small FPGA implementations of low precision polynomial approximations of functions without multipliers. Our method uses degree-2 or degree-3 polynomial approximations with at most 3-bit coefficients and low-precision estimations of the powers of x. Here we denote by 3-bit coefficients values with at most 3 nonzero and possibly noncontiguous signed bits (e.g., 1.0010001~). This leads to very small operators by replacing the costly multipliers by a small number of additions. Our method provides approximations with very low average error and is suitable for signal processing applications.

Divgen: a divider unit generator

In this work, we present a tool that generates division hardware units. This generator, called divgen, allows a fast and wide space exploration in circuits that involve division operations. The generator produces synthesizable VHDL descriptions of optimized division units for various algorithms and parameters. The results of our generator have been demonstrated on FPGA circuits.

Optimisation d'opérateurs arithmétiques matériels à base d'approximations polynomiales

This article presents a method for the optimisation of hardware arithmetic operators dedicated to function evaluation using polynomial approximations. Using recent tools, the method reduces the size of the polynomial coefficients and the intermediate values while keeping the total error bounded (approximation and evaluation). It leads to small and fast operators with a good numerical quality. The method is illustrated on several examples implemented on FPGA circuits.

New identities and transformations for hardware power operators

In this work we present some improvements on hardware operators dedicated to the computation of power operations with fixed integer exponent (x3, x4, . . .) in unsigned radix-2 fixed-point or integer representations. The proposed method reduces the number of partial products using simplifications based on new identities and transformations. These simplifications are performed both at the logical and the arithmetic levels. The proposed method has been implemented in a VHDL generator that produces synthesizable descriptions of optimized operators. The results of our method have been demonstrated on FPGA circuits.