Nicole Wils

Impact of Hot Carriers on nMOSFET Variability in 45- and 65-nm CMOS Technologies

This paper examines the impact of hot carriers (HCs) on n-channel metal-oxide-semiconductor (MOS) field-effect transistor mismatch across the 45- and 65-nm complementary MOS technology generations. The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randomly generated charge traps in the gate dielectric or at the substrate/dielectric interface. The evolution of the threshold-voltage mismatch during an HC stress is well modeled by assuming a Poisson distribution of the induced charge traps with a nonuniform generation along the channel. Once the evolution of the HC-induced VT shift is known, a single parameter is able to accurately describe the evolution of the HC-induced VT variability. This parameter is independent of the stress time and stress bias voltage. The HC stress causes a significantly larger degradation in the subthreshold slope variability, compared to threshold voltage variability for both investigated technology nodes.

High precision on-wafer backend capacitor mismatch measurements using a benchtop semiconductor characterization system

This paper discusses a sophisticated backend capacitor mismatch characterization technique based on direct capacitance measurements with a standard C-V meter, wafer prober subsite moves to measure the two capacitors of each pair sequentially and monitor the measurement noise, and statistics to take this noise appropriately into account. We describe requirements, capabilities and limitations of this approach. It is concluded that this technique proves excellently suited for assessing the matching performance of backend capacitors in the most relevant range of 10 fF to 10 pF.

Parametric Mismatch Characterization for Mixed-Signal Technologies

Systematic and random parametric mismatches are major performance limiters as well as notorious causes for redesigns of high precision mixed-signal circuits and systems. Therefore, it is extremely important to measure, analyze, interpret, model and document parametric mismatch mechanisms meticulously for mixed-signal technologies. This paper gives an overview of the main requirements and techniques for mismatch characterization of active and passive devices in deep submicron mixed-signal IC technologies.

Characterization and Modeling of Hot Carrier-Induced Variability in Subthreshold Region

We developed an analytical model that is able to predict the evolution of the subthreshold slope variability associated with hot carrier (HC) stress. The model assumes that HC stress generates interface states with a Poisson distribution and that the number of HC-induced interface states increases linearly with the HC-induced subthreshold slope variation. We validate the model by means of extensive variability data sets collected on n-channel MOSFETs in 45- and 65-nm CMOS technologies. Furthermore, we investigate the correlation between the threshold voltage and the subthreshold slope fluctuations in order to fully characterize their impact on the subthreshold current variability.

Methodology to evaluate long channel matching deterioration and effects of transistor segmentation on MOSFET matching

This paper summarizes an experimental study on matching of long NMOS transistors and the effects of splitting-up long transistors into series of short transistors. For this purpose, a dedicated set of matched pair test structures were designed and manufactured in a 45 nm CMOS technology. This study is used to evaluate relative threshold voltage matching performance degradations that are observed for long channel devices in such technologies.

Influence of metal coverage on transistor mismatch and variability in copper damascene based CMOS technologies

This paper summarizes a comprehensive study on the effect of asymmetrical metal coverage on matching performance for a 45 nm copper damascene based CMOS process. We demonstrate that random mismatch fluctuations are not affected by metal layout asymmetries and we provide valuable new insights about the magnitude of systematic mismatches that can be expected due to asymmetrical layouts and CMP tiling. For the first time we also present results on the impact of temperature increases on both systematic as well as random drain current mismatches.

Parametric mismatch characterization for mixed-signal technologies

Systematic and random parametric mismatches are major performance limiters as well as notorious causes for re-designs of high precision mixed-signal circuits and systems. Therefore it is extremely important to measure, analyze, interpret, model and document parametric mismatch mechanisms. This paper provides an overview of the main requirements and techniques for mismatch characterization of active and passive IC devices in mixed-signal technologies.

Design and evaluation of an integrated thin film resistor matching test structure

A test structure is presented that combines two types of full Kelvin matched resistor pairs in a single 12 pad process control compatible test line. Based on these structures, matching results of SiCr resistors in a BiCMOS RF technology are discussed, demonstrating some of the frequently encountered challenges of interpreting subtle parametric mismatch fluctuation effects.

Ring-oscillator test-structures for sub-0.1% accuracy wafer-level characterization of active- and standby current consumption, variability, and fast aging of oscillation frequencies

this paper describes a set of ring oscillator test structures, with individually measurable static and dynamic supply currents, Nwell/Pwell leakage currents, and frequency. Purpose is to characterize frequency, leakage and aging and their variabilities, serving the stringent low-energy consumption requirements for IoT products. To obtain a comprehensive technology performance overview, these ring oscillator modules are realized in both GO1 (core oxide, four threshold flavors) and GO2 (I/O oxide, one threshold), either from inverters (mostly) or dual-input NAND/NOR cells, and with channel lengths varying from module to module.

QUBiC generation 9, a new BiCMOS process optimized for mmWave applications

QUBiC generation 9 is NXPs new BiCMOS platform process for high performance RF applications in the mmWave domain. We introduced a new MIM capacitor option and paid special attention to improving the RF noise performance of the HBTs. The extrinsic base resistance has been decreased by several methods, most importantly by self-alignment of the extrinsic base connection to the emitter. The new process is robust and manufacturable and it results in improved noise performance without significantly adding to process complexity. We present results from a discrete transistor that is brought to market to replace GaAs pHEMTs for Ku band LNA applications. The second example is a prototype LNA for the Ka band, NFmin improves with 0.3 dB to 2.5 dB at 30 GHz.