Hans Tuinhout

Analog circuits in ultra-deep-submicron CMOS

Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.

CMOS device optimization for mixed-signal technologies

This paper studies the suitability of CMOS device technology for mixed-signal applications. The currently proposed scaling scenarios for CMOS technologies lead to strong degradation of analog transistor performance. As a result the combined optimization of digital and analog devices for system-on-a-chip applications will require increasingly elaborate process modifications. New device solutions such as metal gate integration and asymmetric (source-side-only) workfunction modification offer process options for future mixed-signal CMOS applications.

The Temperature Dependence of Mismatch in Deep-Submicrometer Bulk MOSFETs

We present a study of the temperature dependence of transistor mismatch in a 65-nm CMOS platform over a temperature range of 0degC to 125degC. We show that the relative-drain-current-mismatch fluctuation properties improve marginally in strong inversion, while they are strongly affected in the subthreshold region. This is compared and explained with a commonly used model. Furthermore, we analyze the change over temperature of the ION mismatch of individual matched pairs. This analysis shows, for the first time, that although relative-current-mismatch fluctuation standard deviations estimated on whole populations are reduced at higher temperatures, the current mismatch of individual pairs can change substantially over temperature.

Impact of Hot Carriers on nMOSFET Variability in 45- and 65-nm CMOS Technologies

This paper examines the impact of hot carriers (HCs) on n-channel metal-oxide-semiconductor (MOS) field-effect transistor mismatch across the 45- and 65-nm complementary MOS technology generations. The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randomly generated charge traps in the gate dielectric or at the substrate/dielectric interface. The evolution of the threshold-voltage mismatch during an HC stress is well modeled by assuming a Poisson distribution of the induced charge traps with a nonuniform generation along the channel. Once the evolution of the HC-induced VT shift is known, a single parameter is able to accurately describe the evolution of the HC-induced VT variability. This parameter is independent of the stress time and stress bias voltage. The HC stress causes a significantly larger degradation in the subthreshold slope variability, compared to threshold voltage variability for both investigated technology nodes.

Impact of interface states on MOS transistor mismatch

Based on modified 2-D drift-diffusion device simulations, mismatch signatures and principal component analysis, this study proves that random interface states fluctuating in terms of density, position and energy levels, in addition to random dopant fluctuations are required for proper interpretation of drain current mismatch in contemporary CMOS technologies.

FinFET Mismatch in Subthreshold Region: Theory and Experiments

In this paper, we study the drain-current mismatch of FinFETs in subthreshold, from both modeling and experimental point of view. We propose a simple model that takes into account the effect of threshold voltage and subthreshold swing fluctuations and their correlation. For long-channel devices (longer than a critical length LC), characterized by a subthreshold swing close to the ideal value, the overall current mismatch is dominated by threshold voltage fluctuations and, therefore, is gate voltage independent. The subthreshold swing fluctuations give a negligible effect on the drain-current mismatch and are uncorrelated with the threshold voltage fluctuations. For short-channel devices (shorter than a critical length LC), characterized by a strong dependence of subthreshold swing on the channel length, the overall current mismatch presents an additional relevant contribution associated with the subthreshold swing fluctuations. This component depends on the gate voltage overdrive and is ascribed to the gate line edge roughness, resulting in a partial correlation between threshold voltage and subthreshold swing fluctuations.

High precision on-wafer backend capacitor mismatch measurements using a benchtop semiconductor characterization system

This paper discusses a sophisticated backend capacitor mismatch characterization technique based on direct capacitance measurements with a standard C-V meter, wafer prober subsite moves to measure the two capacitors of each pair sequentially and monitor the measurement noise, and statistics to take this noise appropriately into account. We describe requirements, capabilities and limitations of this approach. It is concluded that this technique proves excellently suited for assessing the matching performance of backend capacitors in the most relevant range of 10 fF to 10 pF.

Impact of Source/drain Implants on Threshold Voltage Matching in Deep Sub-micron CMOS Technologies

A new mechanism causing deterioration of the threshold voltage matching performance of MOSFETs is described. We demonstrate that this effect depends on several fundamental CMOS device architecture aspects such as the source/drain implant energies, the gate layer thickness, a gate top oxide layer thickness and the poly-silicon gate morphology. It is concluded that penetration of a small (fluctuating) fraction of the LDD and HDD source drain implants through the gate can be responsible for severe degeneration of the matching performance of deep sub-micron CMOS technologies.

Comparison of soft-breakdown triggers for large-area capacitors under constant voltage stress

This work quantitatively compares soft breakdown identification methods for constant voltage stress of large-area nMOS capacitors (up to 10 mm/sup 2/) with 1.8- to 12-nm gate-oxide thickness (with negative gate voltage). We conclude that in the studied range, breakdown is identified more reliably with a current step trigger than through increased current fluctuation. We present a method to quantify the system background noise, and show results of data filtering algorithms that significantly enhance the ratio between the breakdown signal and background noise level.

Parametric Mismatch Characterization for Mixed-Signal Technologies

Systematic and random parametric mismatches are major performance limiters as well as notorious causes for redesigns of high precision mixed-signal circuits and systems. Therefore, it is extremely important to measure, analyze, interpret, model and document parametric mismatch mechanisms meticulously for mixed-signal technologies. This paper gives an overview of the main requirements and techniques for mismatch characterization of active and passive devices in deep submicron mixed-signal IC technologies.